{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T08:21:00Z","timestamp":1725524460744},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540959472"},{"type":"electronic","value":"9783540959489"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-540-95948-9_45","type":"book-chapter","created":{"date-parts":[[2009,1,31]],"date-time":"2009-01-31T10:58:14Z","timestamp":1233399494000},"page":"449-457","source":"Crossref","is-referenced-by-count":1,"title":["Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor"],"prefix":"10.1007","author":[{"given":"Mladen","family":"Berekovic","sequence":"first","affiliation":[]},{"given":"Frank","family":"Bouwens","sequence":"additional","affiliation":[]},{"given":"Tom","family":"Vander Aa","sequence":"additional","affiliation":[]},{"given":"Diederik","family":"Verkest","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"45_CR1","doi-asserted-by":"crossref","unstructured":"Hartenstein, R.: A Decade of Reconfigurable Computing: A Visionary Retrospective. In: Design, Automation and Test in Europe, Conference and Exhibition, 2001. CS Dept. (Informatik), University of Kaiserlautern, Germany, pp. 642\u2013649 (March 2001)","DOI":"10.1109\/DATE.2001.915091"},{"key":"45_CR2","doi-asserted-by":"crossref","unstructured":"Singh, H., Lee, M.-H., Lu, G., Kurdahi, F.J., Bagherzadeh, N.: MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Transactions on Computers, University of California (US) and Federal University of Rio de Janeiro (Brazil), 465\u2013481 (May 2000)","DOI":"10.1109\/12.859540"},{"key":"45_CR3","volume-title":"Fine- and Coarse-Grain Reconfigurable Systems","author":"B. Mei","year":"2007","unstructured":"Mei, B., Berekovic, M., Mignolet, J.-Y.: ADRES & DRESC: Architecture and Compiler for Coarse-Grain Reconfigurable Processors. In: Vassiliadis, S., Soudris, D. (eds.) Fine- and Coarse-Grain Reconfigurable Systems. Springer, Heidelberg (2007)"},{"key":"45_CR4","unstructured":"Mei, B., Vernalde, S., Verkest, D., De Man, H., Lauwereins, R.: ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. In: DATE 2004, IMEC, 2003, Kapeldreef 75, B-3001, Leuven, Belgium (2004)"},{"key":"45_CR5","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/978-3-540-71431-6_1","volume-title":"Reconfigurable Computing: Architectures, Tools and Applications","author":"F. Bouwens","year":"2007","unstructured":"Bouwens, F., Berekovi\u0107, M., Kanstein, A., Gaydadjiev, G.N.: Architectural exploration of the ADRES coarse-grained reconfigurable array. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds.) ARCS 2007. LNCS, vol.\u00a04419, pp. 1\u201313. Springer, Heidelberg (2007)"},{"key":"45_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"66","DOI":"10.1007\/978-3-540-77560-7_6","volume-title":"High Performance Embedded Architectures and Compilers","author":"F. Bouwens","year":"2008","unstructured":"Bouwens, F., Berekovi\u0107, M., De Sutter, B., Gaydadjiev, G.N.: Architecture enhancements for the ADRES coarse-grained reconfigurable array. In: Stenstr\u00f6m, P., Dubois, M., Katevenis, M., Gupta, R., Ungerer, T. (eds.) HiPEAC 2007. LNCS, vol.\u00a04917, pp. 66\u201381. Springer, Heidelberg (2008)"},{"key":"45_CR7","unstructured":"Synopsys, http:\/\/www.synopsys.com"},{"key":"45_CR8","unstructured":"Mentor Graphics, http:\/\/www.mentor.com"},{"key":"45_CR9","unstructured":"Hill, S.: The ARM10 Family of Advanced Microprocessor Cores, HotChips 13, Palo Alto, USA (2001)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-95948-9_45","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,17]],"date-time":"2019-05-17T14:24:09Z","timestamp":1558103049000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-95948-9_45"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783540959472","9783540959489"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-95948-9_45","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}