{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T08:41:39Z","timestamp":1725525699158},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642004537"},{"type":"electronic","value":"9783642004544"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-642-00454-4_18","type":"book-chapter","created":{"date-parts":[[2009,2,18]],"date-time":"2009-02-18T20:00:21Z","timestamp":1234987221000},"page":"171-182","source":"Crossref","is-referenced-by-count":0,"title":["Cache Controller Design on Ultra Low Leakage Embedded Processors"],"prefix":"10.1007","author":[{"given":"Zhao","family":"Lei","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hui","family":"Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Naomi","family":"Seki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Saito","family":"Yoshiki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yohei","family":"Hasegawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kimiyoshi","family":"Usami","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideharu","family":"Amano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"18_CR1","unstructured":"ITRS: AInt\u2019l Technology Roadmap for Semiconductor (2001), http:\/\/public.itrs.net"},{"key":"18_CR2","doi-asserted-by":"crossref","unstructured":"Kaxiras, S., Hu, Z., Martonosi, M.: Cache decay: exploiting generational behavior to reduce cache leakage power. In: Proceedings of the 28th annual international symposium on Computer architecture (2001)","DOI":"10.1145\/379240.379268"},{"key":"18_CR3","doi-asserted-by":"crossref","unstructured":"Kim, N.S., Flautner, K., Blaauw, D., Mudge, T.: Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Transactions on Very Large Scale Integration(VLSI) Systems\u00a012 (2004)","DOI":"10.1109\/TVLSI.2003.821550"},{"key":"18_CR4","doi-asserted-by":"crossref","unstructured":"Hu, Z., Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Jacobson, H., Bose, P.: Microarchitectural techniques for power gating of execution units. In: Proceedings of the 2004 international symposium on Low power electronics and design (2004)","DOI":"10.1145\/1013235.1013249"},{"key":"18_CR5","doi-asserted-by":"crossref","unstructured":"Seki, N., Lei, Z., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Kashima, T., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M., Nakamura, H.: A Fine Grain Dynamic Sleep Control Scheme in MIPS R3000. In: Proceedings of IEEE International Conference on Computer Design 2008 (2008)","DOI":"10.1109\/ICCD.2008.4751924"},{"key":"18_CR6","volume-title":"See MIPS Run","author":"D. Sweetman","year":"2006","unstructured":"Sweetman, D.: See MIPS Run. Morgan Kaufmann, San Francisco (2006)"},{"key":"18_CR7","doi-asserted-by":"crossref","unstructured":"Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, M., Amano, H., Namiki, M., Imai, M., Kondo, M., Nakamura, H.: Design and Implementation of Fine-grain Power Gating with Ground Bounce Suppression. In: IEEE International Conference on VLSI design 2009 (to appear) (2009)","DOI":"10.1109\/VLSI.Design.2009.63"},{"key":"18_CR8","doi-asserted-by":"crossref","unstructured":"Usami, K., Ohkubo, N.: A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. In: IEEE International Conference on Computer Design 2006 (2006)","DOI":"10.1109\/ICCD.2006.4380809"},{"key":"18_CR9","volume-title":"Computer Architecture: A Quantitative Approach","author":"J.L. Hennessy","year":"2003","unstructured":"Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 4th edn. Morgan Kaufmann, San Francisco (2003)","edition":"4"},{"key":"18_CR10","doi-asserted-by":"crossref","unstructured":"Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, M.T., Mudge, T., Brown, B.R.: MiBench: A free, commercially representative embedded benchmark suite. In: 2001 IEEE International Workshop on Workload Characterization (2001)","DOI":"10.1109\/WWC.2001.990739"}],"container-title":["Lecture Notes in Computer Science","Architecture of Computing Systems \u2013 ARCS 2009"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-00454-4_18","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,17]],"date-time":"2019-05-17T23:51:41Z","timestamp":1558137101000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-00454-4_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783642004537","9783642004544"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-00454-4_18","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}