{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:34:15Z","timestamp":1761647655789},"publisher-location":"Berlin, Heidelberg","reference-count":6,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642004537"},{"type":"electronic","value":"9783642004544"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-642-00454-4_8","type":"book-chapter","created":{"date-parts":[[2009,2,19]],"date-time":"2009-02-19T01:00:21Z","timestamp":1235005221000},"page":"50-59","source":"Crossref","is-referenced-by-count":6,"title":["SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs"],"prefix":"10.1007","author":[{"given":"Bj\u00f6rn","family":"Osterloh","sequence":"first","affiliation":[]},{"given":"Harald","family":"Michalik","sequence":"additional","affiliation":[]},{"given":"Bj\u00f6rn","family":"Fiethe","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"8_CR1","first-page":"977","volume-title":"Proceedings of the conference on Design, automation and test in Europe (DATE)","author":"B. Fiethe","year":"2007","unstructured":"Fiethe, B., Michalik, H., Dierker, C., Osterloh, B., Zhou, G.: Reconfigurable System-on-Chip Data Processing Units for Miniaturized Space Imaging Instruments. In: Proceedings of the conference on Design, automation and test in Europe (DATE), pp. 977\u2013982. ACM, New York (2007)"},{"key":"8_CR2","doi-asserted-by":"crossref","unstructured":"Osterloh, B., Michalik, H., Fiethe, B., Bubenhagen, F.: Enhancements of reconfigurable System-on-Chip Data Processing Units for Space Application. In: Second NASA\/ESA Conference on Adaptive Hardware and Systems (AHS 2007), Edinburgh, pp. 258\u2013262 (August 2007)","DOI":"10.1109\/AHS.2007.47"},{"key":"8_CR3","unstructured":"Xilinx, Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description (September 2005), \n                    \n                      www.xilinx.com"},{"key":"8_CR4","unstructured":"Xilinx, Virtex-4 Configuration Guide (October 2007), \n                    \n                      www.xilinx.com"},{"key":"8_CR5","doi-asserted-by":"publisher","DOI":"10.1007\/b105353","volume-title":"Networks on Chip","author":"A. Jantsch","year":"2003","unstructured":"Jantsch, A., Tenhunen, H.: Networks on Chip. Kluwer Academic Publishers, USA (2003)"},{"key":"8_CR6","unstructured":"ECSS, Space Engineering: SpaceWire\u2013Links, nodes, routers, and networks, ESA-ESTEC, Noordwijk Netherlands, ECSS-E-50-12A (January 2003)"}],"container-title":["Lecture Notes in Computer Science","Architecture of Computing Systems \u2013 ARCS 2009"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-00454-4_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,3,5]],"date-time":"2019-03-05T21:00:56Z","timestamp":1551819656000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-00454-4_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783642004537","9783642004544"],"references-count":6,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-00454-4_8","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}