{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T09:30:31Z","timestamp":1725528631942},"publisher-location":"Berlin, Heidelberg","reference-count":21,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642006401"},{"type":"electronic","value":"9783642006418"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-642-00641-8_16","type":"book-chapter","created":{"date-parts":[[2009,3,6]],"date-time":"2009-03-06T13:41:46Z","timestamp":1236346906000},"page":"145-156","source":"Crossref","is-referenced-by-count":1,"title":["On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks"],"prefix":"10.1007","author":[{"given":"Ricardo","family":"Ferreira","sequence":"first","affiliation":[]},{"given":"Alex","family":"Damiany","sequence":"additional","affiliation":[]},{"given":"Julio","family":"Vendramini","sequence":"additional","affiliation":[]},{"given":"Tiago","family":"Teixeira","sequence":"additional","affiliation":[]},{"given":"Jo\u00e3o M. P.","family":"Cardoso","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"16_CR1","volume-title":"Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation","author":"S. Hauck","year":"2007","unstructured":"Hauck, S., DeHon, A.: Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann, San Francisco (2007)"},{"issue":"2","key":"16_CR2","doi-asserted-by":"publisher","first-page":"90","DOI":"10.1109\/MDT.2005.27","volume":"22","author":"B. Mei","year":"2005","unstructured":"Mei, B., Lambrechts, A., Verkest, D., Mignolet, J.Y., Lauwereins, R.: Architecture exploration for a reconfigurable architecture template. IEEE Des. Test\u00a022(2), 90\u2013101 (2005)","journal-title":"IEEE Des. Test"},{"issue":"2","key":"16_CR3","doi-asserted-by":"publisher","first-page":"167","DOI":"10.1023\/A:1024499601571","volume":"26","author":"E. Volker Baumgarten","year":"2003","unstructured":"Volker Baumgarten, E.: PACT XPP - A Self-Reconfigurable Data Processing Architecture. The Journal of Supercomputing (TJS)\u00a026(2), 167\u2013184 (2003)","journal-title":"The Journal of Supercomputing (TJS)"},{"key":"16_CR4","doi-asserted-by":"crossref","unstructured":"Lawrie, D.H.: Access and alignment of data in an array processor. IEEE Trans. Comput.\u00a024(12) (1975)","DOI":"10.1109\/T-C.1975.224157"},{"key":"16_CR5","doi-asserted-by":"publisher","first-page":"642","DOI":"10.1109\/DATE.2001.915091","volume-title":"DATE 2001: Proceedings of the conference on Design, automation and test in Europe","author":"R. Hartenstein","year":"2001","unstructured":"Hartenstein, R.: A decade of reconfigurable computing: a visionary retrospective. In: DATE 2001: Proceedings of the conference on Design, automation and test in Europe, pp. 642\u2013649. IEEE Press, Piscataway (2001)"},{"key":"16_CR6","first-page":"10474","volume-title":"DATE 2004: Proceedings of the conference on Design, automation and test in Europe","author":"N. Bansal","year":"2004","unstructured":"Bansal, N., Gupta, S., Dutt, N., Nicolau, A., Gupta, R.: Network topology exploration of mesh-based coarse-grain reconfigurable architectures. In: DATE 2004: Proceedings of the conference on Design, automation and test in Europe, p. 10474. IEEE Computer Society, Washington (2004)"},{"issue":"11","key":"16_CR7","doi-asserted-by":"publisher","first-page":"1361","DOI":"10.1109\/12.177307","volume":"41","author":"Y.M. Yeh","year":"1992","unstructured":"Yeh, Y.M., yun Feng, T.: On a class of rearrangeable networks. IEEE Trans. Comput.\u00a041(11), 1361\u20131379 (1992)","journal-title":"IEEE Trans. Comput."},{"issue":"10","key":"16_CR8","doi-asserted-by":"publisher","first-page":"1057","DOI":"10.1109\/TCOM.1977.1093753","volume":"25","author":"S. Andresen","year":"1977","unstructured":"Andresen, S.: The looping algorithm extended to base 2t rearrangeable switching networks. IEEE Trans. Commun.\u00a025(10), 1057\u20131063 (1977)","journal-title":"IEEE Trans. Commun."},{"issue":"1","key":"16_CR9","doi-asserted-by":"publisher","first-page":"97","DOI":"10.1109\/12.481490","volume":"45","author":"Q. Hu","year":"1996","unstructured":"Hu, Q., Shen, X., Liang, W.: Optimally routing lc permutations on k-extra-stage cube-type networks. IEEE Trans. Comput.\u00a045(1), 97\u2013103 (1996)","journal-title":"IEEE Trans. Comput."},{"key":"16_CR10","doi-asserted-by":"publisher","first-page":"321","DOI":"10.1145\/1366110.1366186","volume-title":"GLSVLSI 2008: Proceedings of the 18th ACM Great Lakes symposium on VLSI","author":"M. Zied","year":"2008","unstructured":"Zied, M., Hayder, M., Emna, A., Habib, M.: Efficient tree topology for fpga interconnect network. In: GLSVLSI 2008: Proceedings of the 18th ACM Great Lakes symposium on VLSI, pp. 321\u2013326. ACM, New York (2008)"},{"issue":"2","key":"16_CR11","doi-asserted-by":"publisher","first-page":"126","DOI":"10.1145\/1273440.1250679","volume":"35","author":"J. Kim","year":"2007","unstructured":"Kim, J., Dally, W.J., Abts, D.: Flattened butterfly: a cost-efficient topology for high-radix networks. SIGARCH Comput. Archit. News\u00a035(2), 126\u2013137 (2007)","journal-title":"SIGARCH Comput. Archit. News"},{"key":"16_CR12","first-page":"205","volume-title":"FCCM 2002: Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","author":"A. DeHon","year":"2002","unstructured":"DeHon, A., Huang, R., Wawrzynek, J.: Hardware-assisted fast routing. In: FCCM 2002: Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p. 205. IEEE Computer Society, Washington (2002)"},{"key":"16_CR13","volume-title":"Mathematical Theory of Connecting Networks and Telephone Traffic","author":"V.E. Benes","year":"1965","unstructured":"Benes, V.E.: Mathematical Theory of Connecting Networks and Telephone Traffic. Academic Press, New York (1965)"},{"issue":"6","key":"16_CR14","first-page":"768","volume":"36","author":"K.Y. Lee","year":"1987","unstructured":"Lee, K.Y.: A new benes network control algorithm. IEEE Trans. Comput.\u00a036(6), 768\u2013772 (1987)","journal-title":"IEEE Trans. Comput."},{"key":"16_CR15","first-page":"28","volume-title":"ISCA 1999: Proceedings of the 26th annual international symposium on Computer architecture","author":"S.C. Goldstein","year":"1999","unstructured":"Goldstein, S.C., Schmit, H., Moe, M., Budiu, M., Cadambi, S., Taylor, R.R., Laufer, R.: Piperench: a co\/processor for streaming multimedia acceleration. In: ISCA 1999: Proceedings of the 26th annual international symposium on Computer architecture, pp. 28\u201339. IEEE Computer Society, Washington (1999)"},{"key":"16_CR16","unstructured":"Tessier, R.G.: Fast Place and Route Approaches for FPGAs. Phd thesis, MIT, Massachusetts Institute of Technology (1999)"},{"key":"16_CR17","first-page":"10296","volume-title":"DATE 2003: Proceedings of the conference on Design, Automation and Test in Europe","author":"B. Mei","year":"2003","unstructured":"Mei, B., Vernalde, S., Verkest, D., Man, H.D., Lauwereins, R.: Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling. In: DATE 2003: Proceedings of the conference on Design, Automation and Test in Europe, p. 10296. IEEE Computer Society, Washington (2003)"},{"key":"16_CR18","first-page":"61","volume-title":"ISVLSI","author":"R. Ferreira","year":"2007","unstructured":"Ferreira, R., Garcia, A., Teixeira, T., Cardoso, J.M.P.: A polynomial placement algorithm for data driven coarse-grained reconfigurable architectures. In: ISVLSI, pp. 61\u201366. IEEE Computer Society, Los Alamitos (2007)"},{"key":"16_CR19","unstructured":"ExPRESS Benchmarks: Electrical & Computer Engineering Department at the UCSB, USA (last access on November 3rd 2008), \n                    \n                      http:\/\/express.ece.ucsb.edu\/benchmark\/"},{"key":"16_CR20","first-page":"1","volume-title":"Parallel and Distributed Processing Symposium, International","author":"G. Mehta","year":"2007","unstructured":"Mehta, G., Stander, J., Baz, M., Hunsaker, B., Jones, A.K.: Interconnect customization for a coarse-grained reconfigurable fabric. In: Parallel and Distributed Processing Symposium, International, pp. 1\u20138. IEEE Computer Society, Los Alamitos (2007)"},{"key":"16_CR21","first-page":"954","volume-title":"DAC 2004: Proceedings of the 41st annual conference on Design automation","author":"R. Lysecky","year":"2004","unstructured":"Lysecky, R., Vahid, F., Tan, S.X.D.: Dynamic fpga routing for just-in-time fpga compilation. In: DAC 2004: Proceedings of the 41st annual conference on Design automation, pp. 954\u2013959. ACM, New York (2004)"}],"container-title":["Lecture Notes in Computer Science","Reconfigurable Computing: Architectures, Tools and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-00641-8_16","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,3,6]],"date-time":"2019-03-06T10:22:03Z","timestamp":1551867723000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-00641-8_16"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783642006401","9783642006418"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-00641-8_16","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}