{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T09:30:39Z","timestamp":1725528639510},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642006401"},{"type":"electronic","value":"9783642006418"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-642-00641-8_25","type":"book-chapter","created":{"date-parts":[[2009,3,6]],"date-time":"2009-03-06T08:41:46Z","timestamp":1236328906000},"page":"255-260","source":"Crossref","is-referenced-by-count":5,"title":["SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems"],"prefix":"10.1007","author":[{"given":"Jos\u00e9 M.","family":"Moya","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Javier","family":"Rodr\u00edguez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Julio","family":"Mart\u00edn","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Juan Carlos","family":"Vallejo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pedro","family":"Malag\u00f3n","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"\u00c1lvaro","family":"Araujo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Juan-Mariano","family":"de Goyeneche","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Agust\u00edn","family":"Rubio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Elena","family":"Romero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Villanueva","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Octavio","family":"Nieto-Taladriz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Carlos A.","family":"L\u00f3pez Barrio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"25_CR1","doi-asserted-by":"publisher","first-page":"23","DOI":"10.1109\/FPGA.1994.315595","volume-title":"IEEE Workshop on FPGAs for Custom Computing Machines","author":"M.J. Wirthlin","year":"1994","unstructured":"Wirthlin, M.J., Hutchings, B.L., Gilson, K.L.: The nano processor: A low resource reconfigurable processor. In: Buell, D.A., Pocek, K.L. (eds.) IEEE Workshop on FPGAs for Custom Computing Machines, pp. 23\u201330. IEEE Computer Society Press, Los Alamitos (1994)"},{"doi-asserted-by":"crossref","unstructured":"Razdan, R., Smith, M.D.: A high-performance microarchitecture with hardware-programmable functional units. In: Proceedings of the 27th Annual International Symposium on Microarchitecture, pp. 172\u201380 (1994)","key":"25_CR2","DOI":"10.1145\/192724.192749"},{"key":"25_CR3","doi-asserted-by":"publisher","first-page":"99","DOI":"10.1109\/FPGA.1995.477415","volume-title":"IEEE Symposium on FPGAs for Custom Computing Machines","author":"M. Wirthlin","year":"1995","unstructured":"Wirthlin, M., Hutchings, B.: A dynamic instruction set computer. In: Athanas, P., Pocek, K.L. (eds.) IEEE Symposium on FPGAs for Custom Computing Machines, pp. 99\u2013107. IEEE Computer Society Press, Los Alamitos (1995)"},{"issue":"2","key":"25_CR4","doi-asserted-by":"publisher","first-page":"206","DOI":"10.1109\/TVLSI.2003.821545","volume":"12","author":"S. Hauck","year":"2004","unstructured":"Hauck, S., Fry, T.W., Hosler, M.M., Kao, J.P.: The chimaera reconfigurable functional unit. IEEE Trans. Very Large Scale Integr. Syst.\u00a012(2), 206\u2013217 (2004)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"25_CR5","doi-asserted-by":"publisher","first-page":"145","DOI":"10.1145\/296399.296446","volume-title":"FPGA 1999: Proceedings of the 1999 ACM\/SIGDA seventh international symposium on Field programmable gate arrays","author":"J.A. Jacob","year":"1999","unstructured":"Jacob, J.A., Chow, P.: Memory interfacing and instruction specification for reconfigurable processors. In: FPGA 1999: Proceedings of the 1999 ACM\/SIGDA seventh international symposium on Field programmable gate arrays, pp. 145\u2013154. ACM Press, New York (1999)"},{"key":"25_CR6","first-page":"28","volume-title":"ISCA 1999: Proceedings of the 26th annual international symposium on Computer architecture","author":"S.C. Goldstein","year":"1999","unstructured":"Goldstein, S.C., Schmit, H., Moe, M., Budiu, M., Cadambi, S., Taylor, R.R., Laufer, R.: PipeRench: a co\/processor for streaming multimedia acceleration. In: ISCA 1999: Proceedings of the 26th annual international symposium on Computer architecture, pp. 28\u201339. IEEE Computer Society, Washington (1999)"},{"key":"25_CR7","first-page":"141","volume-title":"MICRO 36: Proceedings of the 36th annual IEEE\/ACM International Symposium on Microarchitecture","author":"S. Ciricescu","year":"2003","unstructured":"Ciricescu, S., Essick, R., Lucas, B., May, P., Moat, K., Norris, J., Schuette, M., Saidi, A.: The reconfigurable streaming vector processor (rsvptm). In: MICRO 36: Proceedings of the 36th annual IEEE\/ACM International Symposium on Microarchitecture, p. 141. IEEE Computer Society, Washington (2003)"},{"doi-asserted-by":"crossref","unstructured":"Lattner, C., Adve, V.: LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation. In: Proceedings of the 2004 International Symposium on Code Generation and Optimization (CGO 2004), Palo Alto, California (March 2004)","key":"25_CR8","DOI":"10.1109\/CGO.2004.1281665"},{"key":"25_CR9","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"87","DOI":"10.1007\/11587514_7","volume-title":"High Performance Embedded Architectures and Compilers","author":"K. Ning","year":"2005","unstructured":"Ning, K., Kaeli, D.: Power aware external bus arbitration for system-on-a-chip embedded systems. In: Conte, T., Navarro, N., Hwu, W.-m.W., Valero, M., Ungerer, T. (eds.) HiPEAC 2005. LNCS, vol.\u00a03793, pp. 87\u2013101. Springer, Heidelberg (2005)"},{"key":"25_CR10","volume-title":"WVLSI 2000: Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI 2000)","author":"H.S. Kim","year":"2000","unstructured":"Kim, H.S., Narayanan, V., Kandemir, M., Irwin, M.J.: Multiple access caches: Energy implications. In: WVLSI 2000: Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI 2000). IEEE Computer Society, Washington (2000)"}],"container-title":["Lecture Notes in Computer Science","Reconfigurable Computing: Architectures, Tools and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-00641-8_25","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,18]],"date-time":"2019-05-18T09:46:54Z","timestamp":1558172814000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-00641-8_25"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783642006401","9783642006418"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-00641-8_25","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}