{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T09:30:09Z","timestamp":1725528609639},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642006401"},{"type":"electronic","value":"9783642006418"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-642-00641-8_28","type":"book-chapter","created":{"date-parts":[[2009,3,6]],"date-time":"2009-03-06T08:41:46Z","timestamp":1236328906000},"page":"275-280","source":"Crossref","is-referenced-by-count":2,"title":["The Need for Reconfigurable Routers in Networks-on-Chip"],"prefix":"10.1007","author":[{"given":"Debora","family":"Matos","sequence":"first","affiliation":[]},{"given":"Caroline","family":"Concatto","sequence":"additional","affiliation":[]},{"given":"Luigi","family":"Carro","sequence":"additional","affiliation":[]},{"given":"Fernanda","family":"Kastensmidt","sequence":"additional","affiliation":[]},{"given":"Altamiro","family":"Susin","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"28_CR1","doi-asserted-by":"crossref","unstructured":"Benini, L., De Micheli, G.: Network on Chips: A new SoC Paradigm. IEEE Computer, 70\u201378 (2002)","DOI":"10.1109\/2.976921"},{"issue":"5","key":"28_CR2","doi-asserted-by":"publisher","first-page":"808","DOI":"10.1109\/JPROC.2008.917730","volume":"96","author":"J. Manferdelli","year":"2008","unstructured":"Manferdelli, J., Govindaraju, N., Crall, C.: Challenges and Opportunities in Many-Core Computing. Proceeding of the IEEE\u00a096(5), 808\u2013815 (2008)","journal-title":"Proceeding of the IEEE"},{"issue":"2","key":"28_CR3","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1109\/MM.2006.45","volume":"26","author":"J. Andrews","year":"2006","unstructured":"Andrews, J., Baker, N.: Xbox 360 System Architecture. IEEE Micro\u00a026(2), 25\u201337 (2006)","journal-title":"IEEE Micro"},{"key":"28_CR4","doi-asserted-by":"crossref","unstructured":"Cardoso, R., Kreutz, M., Carro, S., Susin, A.: Design Space Exploration on Heterogeneous Network-on-chip. In: International Symposium on Circuits and Systems, vol. 1, pp. 428\u2013431 (2005)","DOI":"10.1109\/ISCAS.2005.1464616"},{"key":"28_CR5","doi-asserted-by":"crossref","unstructured":"Kreutz, M., Marcon, C., Carro, L., Wagner, F., Susin, A.: Design Space Exploration Comparing Homogenous and Heterogeneous Network-on-Chip Architectures. In: Symposium on Integrated Circuits and Systems Design, SBCCI 2005, pp. 190\u2013195 (2005)","DOI":"10.1109\/SBCCI.2005.4286855"},{"key":"28_CR6","doi-asserted-by":"crossref","unstructured":"Ahmad, B., Ahmadinia, A., Arslan, T.: Dynamically Reconfigurable NOC with Bus Based Interface for Ease of Integration and Reduced Designed Time. In: NASA\/ESA Conference on Adaptive Hardware and Systems (AHS 2008), pp. 309\u2013314 (2008)","DOI":"10.1109\/AHS.2008.38"},{"key":"28_CR7","doi-asserted-by":"crossref","unstructured":"Ahonen, T., Nurmi, J.: Hierarchically Heterogeneous Network-on-Chip. In: The International Conference on Computer as a Tool, EUROCON, pp. 2580\u20132586 (2007)","DOI":"10.1109\/EURCON.2007.4400469"},{"key":"28_CR8","doi-asserted-by":"crossref","unstructured":"Eun Lee, S., Bagherzadeh, N.: Increasing the Throughput of an Adaptive Router in Network-on-Chip (NoC). In: International Conference on Hardware\/ Software Codesign and System Synthesis, pp. 82\u201387 (2006)","DOI":"10.1145\/1176254.1176276"},{"key":"28_CR9","doi-asserted-by":"crossref","unstructured":"Wu, C., Chi, H.: Design of a High-Performance Switch for Circuit-Switched On-Chip Networks. In: Asian Solid-State Circuits Conference, pp. 481\u2013484 (2005)","DOI":"10.1109\/ASSCC.2005.251770"},{"key":"28_CR10","doi-asserted-by":"crossref","unstructured":"Varatkar, G.V., Marculescu, R.: On-chip traffic modeling and synthesis for MPEG-2 video applications. IEEE Transactions on Very Large Scale Integration (VLSI) System, 108\u2013119 (2004)","DOI":"10.1109\/TVLSI.2003.820523"}],"container-title":["Lecture Notes in Computer Science","Reconfigurable Computing: Architectures, Tools and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-00641-8_28","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,18]],"date-time":"2019-05-18T09:46:39Z","timestamp":1558172799000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-00641-8_28"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783642006401","9783642006418"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-00641-8_28","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}