{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T09:30:21Z","timestamp":1725528621566},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642006401"},{"type":"electronic","value":"9783642006418"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-642-00641-8_4","type":"book-chapter","created":{"date-parts":[[2009,3,6]],"date-time":"2009-03-06T08:41:46Z","timestamp":1236328906000},"page":"4-14","source":"Crossref","is-referenced-by-count":1,"title":["A HyperTransport 3 Physical Layer Interface for FPGAs"],"prefix":"10.1007","author":[{"given":"Heiner","family":"Litz","sequence":"first","affiliation":[]},{"given":"Holger","family":"Froening","sequence":"additional","affiliation":[]},{"given":"Ulrich","family":"Bruening","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"4_CR1","volume-title":"HyperTransport System Architecture","author":"D. Anderson","year":"2003","unstructured":"Anderson, D., Trodden, J.: HyperTransport System Architecture. Addison-Wesley, Reading (2003)"},{"key":"4_CR2","unstructured":"Hypertransport Consortium, The Future of High-Performance Computing: Direct Low Latency CPU-to-Subsystem Interconnect (2008), \n                    \n                      http:\/\/www.hypertransport.org"},{"issue":"2","key":"4_CR3","doi-asserted-by":"publisher","first-page":"66","DOI":"10.1109\/MM.2003.1196116","volume":"23","author":"C.N. Keltcher","year":"2003","unstructured":"Keltcher, C.N., McGrath, K.J., Ahmed, A., Conway, P.: The AMD Opteron proc\u00acessor for multiprocessor servers. IEEE Micro.\u00a023(2), 66\u201367 (2003)","journal-title":"IEEE Micro."},{"key":"4_CR4","unstructured":"Hypertransport Consortium. HyperTransportTM I\/O Link Specification Revision 3.10 (2008), \n                    \n                      http:\/\/www.hypertransport.org"},{"key":"4_CR5","unstructured":"HyperTransport Consortium. HTX3TM Specification for HyperTransportTM 3.0 Daughtercards and ATX\/EATX Motherboards (2008), \n                    \n                      http:\/\/www.hypertransport.org"},{"issue":"2","key":"4_CR6","doi-asserted-by":"publisher","first-page":"10","DOI":"10.1109\/MM.2007.43","volume":"27","author":"P. Conway","year":"2007","unstructured":"Conway, P., Hughes, B.: The AMD Opteron Northbridge Architecture. IEEE Micro.\u00a027(2), 10\u201321 (2007)","journal-title":"IEEE Micro."},{"key":"4_CR7","doi-asserted-by":"publisher","first-page":"4","DOI":"10.1016\/j.parco.2008.01.009","volume":"34","author":"A. Gothandaraman","year":"2008","unstructured":"Gothandaraman, A., Peterson, G.D., Warren, G.L., Hinde, R.J., Harrison, R.J.: FPGA acceleration of a quantum Monte Carlo application. Parallel Computing\u00a034, 4\u20135 (2008)","journal-title":"Parallel Computing"},{"key":"4_CR8","doi-asserted-by":"crossref","unstructured":"Zhuo, L., Prasanna, V.K.: High Performance Linear Algebra Operations on Reconfigurable Systems. In: Proceedings of the 2005 ACM\/IEEE Conference on Supercomputing (2005)","DOI":"10.1109\/SC.2005.31"},{"key":"4_CR9","doi-asserted-by":"crossref","unstructured":"Litz, H., Froening, H., Nuessle, M., Bruening, U.: VELO: A Novel Com\u00acmunication Engine for Ultra-low Latency Message Transfers. In: 37th International Conference on Parallel Processing (ICPP 2008), Portland, Oregon, USA, September 08 - 12 (2008)","DOI":"10.1109\/ICPP.2008.85"},{"key":"4_CR10","series-title":"Wiley Series on Parallel and Distributed Computing","doi-asserted-by":"publisher","DOI":"10.1002\/0471478369","volume-title":"UPC: Distributed Sharend Memory Programming","author":"T. El-Ghazawi","year":"2005","unstructured":"El-Ghazawi, T., Carlson, W., Sterling, T., Yelick, K.: UPC: Distributed Sharend Memory Programming. Wiley Series on Parallel and Distributed Computing. John Wiley and Sons, Inc., Hoboken (2005)"},{"issue":"3","key":"4_CR11","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1391732.1391734","volume":"1","author":"D. Slogsnat","year":"2008","unstructured":"Slogsnat, D., Giese, A., Nuessle, M., Bruening, U.: An Open-Source HyperTransport Core. ACM Transactions on Reconfigurable Technology and Systems (TRETS)\u00a01(3), 1\u201321 (2008)","journal-title":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)"}],"container-title":["Lecture Notes in Computer Science","Reconfigurable Computing: Architectures, Tools and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-00641-8_4","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,3,6]],"date-time":"2019-03-06T07:07:43Z","timestamp":1551856063000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-00641-8_4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783642006401","9783642006418"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-00641-8_4","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}