{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T10:07:49Z","timestamp":1725530869138},"publisher-location":"Berlin, Heidelberg","reference-count":26,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642009037"},{"type":"electronic","value":"9783642009044"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-642-00904-4_7","type":"book-chapter","created":{"date-parts":[[2009,4,21]],"date-time":"2009-04-21T02:39:49Z","timestamp":1240281589000},"page":"107-127","source":"Crossref","is-referenced-by-count":0,"title":["Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors"],"prefix":"10.1007","author":[{"given":"Woojin","family":"Choi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seok-Jun","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michel","family":"Dubois","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"7_CR1","doi-asserted-by":"crossref","unstructured":"Agarwal, V., Hrishikesh, M., Keckler, S., Burger, D.: Clock Rate versus IPC: The End of the Road for Conventional Microprocessors. In: Proceedings of the 27th International Symposium on Computer Architecture (2000)","DOI":"10.1145\/339647.339691"},{"key":"7_CR2","doi-asserted-by":"crossref","unstructured":"Hrishikesh, M., Jouppi, N., Farkas, K., Burger, D., Keckler, S., Shivakumar, P.: The Optimal Logic Depth per Pipeline Stage is 6 to 8 FO4 Inverter Delays. In: Proceedings of the 29th International Symposium on Computer Architecture (2002)","DOI":"10.1109\/ISCA.2002.1003558"},{"key":"7_CR3","doi-asserted-by":"crossref","unstructured":"Stark, J., Brown, M., Patt, Y.: On Pipelining Dynamic Instruction Sched\u00aculing Logic. In: Proceedings of the 33rd International Symposium on Microarchitecture (2000)","DOI":"10.1145\/360128.360136"},{"key":"7_CR4","doi-asserted-by":"crossref","unstructured":"Michaud, P., Seznec, A.: Data-Flow Prescheduling for Large Issue queues in Out-of-Order Processors. In: Proceedings of the 7th International Symposium on High Performance Computer Architecture (2001)","DOI":"10.1109\/HPCA.2001.903249"},{"key":"7_CR5","doi-asserted-by":"crossref","unstructured":"Raasch, S., Binkert, N., Reinhardt, S.: A Scalable Instruction Queue De\u00acsign Using Dependence Chains. In: Proceedings of the 29th International Symposium on Computer Architecture (2002)","DOI":"10.1145\/545214.545251"},{"key":"7_CR6","doi-asserted-by":"crossref","unstructured":"Liu, Y., Shayesteh, A., Memik, G., Reinman, G.: Scaling the Issue Window with Look-Ahead Latency Prediction. In: Proceedings of the 18th Annual ACM International Conference on Supercomputing (2004)","DOI":"10.1145\/1006209.1006240"},{"key":"7_CR7","doi-asserted-by":"crossref","unstructured":"Liu, Y., Shayesteh, A., Memik, G., Reinman, G.: Tornado Warning: the Perils of Selective Replay in Multithreaded Processors. In: Proceedings of the 19th Annual ACM International Conference on Supercomputing (2005)","DOI":"10.1145\/1088149.1088157"},{"key":"7_CR8","doi-asserted-by":"crossref","unstructured":"Canal, R., Gonz\u00e1lez, A.: Reducing the Complexity of the Issue Logic. In: Proceedings of the 15th International Conference on Supercomputing (2001)","DOI":"10.1145\/377792.377854"},{"key":"7_CR9","doi-asserted-by":"crossref","unstructured":"Ernst, D., Hamel, A., Austin, T.: Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay. In: Proceedings of the 30th International Symposium on Computer Architecture (2003)","DOI":"10.1145\/859618.859647"},{"key":"7_CR10","doi-asserted-by":"crossref","unstructured":"Hu, J., Vijaykrishnan, N., Irwin, M.: Exploring Wakeup-Free Instruction Scheduling. In: Proceedings of the 10th International Symposium on High Performance Computer Architecture (2004)","DOI":"10.1109\/HPCA.2004.10014"},{"key":"7_CR11","unstructured":"Kim, I., Lipasti, M.: Understanding Scheduling Replay Schemes. In: Proceedings of the 10th International Symposium on High Performance Computer Architecture (2004)"},{"key":"7_CR12","doi-asserted-by":"crossref","unstructured":"Yoaz, A., Erez, M., Ronen, R., Jourdan, S.: Speculation Techniques for Improving Load Related Instruction Scheduling. In: Proceedings of the 26th International Symposium on Computer Architecture (1999)","DOI":"10.1109\/ISCA.1999.765938"},{"key":"7_CR13","unstructured":"Merchant, A., Sagar, D.: Computer Processor Having a Checker. United States Patent #6,212,626, assigned to Intel Corporation, issued April 3 (2001)"},{"key":"7_CR14","doi-asserted-by":"crossref","unstructured":"Chrysos, G., Emer, J.: Memory Dependence Prediction Using Store Sets. In: Proceedings of the 25th International Symposium on Computer Architecture (1998)","DOI":"10.1109\/ISCA.1998.694770"},{"key":"7_CR15","doi-asserted-by":"crossref","unstructured":"Kessler, R.: The Alpha 21264 Microprocessor. IEEE Micro.\u00a019(2), 24-36(1999)","DOI":"10.1109\/40.755465"},{"key":"7_CR16","doi-asserted-by":"crossref","unstructured":"Tendler, J., Dodson, S., Fields, S., Le, H., Sinharoy, B.: Power4 System Microarchitecture. IBM Journal of Research and Development\u00a046(1), 5\u201326 (2002)","DOI":"10.1147\/rd.461.0005"},{"key":"7_CR17","unstructured":"Hinton, G., Sager, D., Upton, M., Boggs, D., Carmean, D., Kyker, A., Roussel, P.: The Microarchitecture of the Pentium 4 Processor. Intel Technology Journal, Q1 (2001)"},{"key":"7_CR18","doi-asserted-by":"crossref","unstructured":"Lebeck, A., Koppanalil, J., Li, T., Patwardhan, J., Rotenberg, E.: A Large, Fast Instruction Window for Tolerating Cache Misses. In: Proceedings of the 29th International Symposium on Computer Architecture (2002)","DOI":"10.1109\/ISCA.2002.1003562"},{"key":"7_CR19","doi-asserted-by":"crossref","unstructured":"Palacharla, S., Jouppi, N., Smith, J.: Complexity-Effective Superscalar Processors. In: Proceedings of the 24th International Symposium on Computer Architecture (1997)","DOI":"10.1145\/264107.264201"},{"issue":"1","key":"7_CR20","doi-asserted-by":"publisher","first-page":"42","DOI":"10.1109\/2.976918","volume":"35","author":"A. Allan","year":"2002","unstructured":"Allan, A., Edenfeld, D., Joyner, W., Kahng, A., Rodgers, M., Zorian, Y.: 2001 Technology Roadmap for Semiconductors. IEEE Computer\u00a035(1), 42\u201353 (2002)","journal-title":"IEEE Computer"},{"issue":"2","key":"7_CR21","doi-asserted-by":"publisher","first-page":"59","DOI":"10.1109\/2.982917","volume":"35","author":"T. Austin","year":"2002","unstructured":"Austin, T., Larson, E., Ernst, D.: SimpleScalar: an Infrastructure for Computer System Modeling. IEEE Computer\u00a035(2), 59\u201367 (2002)","journal-title":"IEEE Computer"},{"key":"7_CR22","unstructured":"Standard Performance Evaluation Corporation, http:\/\/www.specbench.org"},{"key":"7_CR23","doi-asserted-by":"crossref","unstructured":"Sherwood, T., Perelman, E., Hamerly, G., Calder, B.: Automatically Char\u00acacterizing Large Scale Program Behavior. In: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (2002)","DOI":"10.1145\/605402.605403"},{"key":"7_CR24","unstructured":"Synopsys Inc., http:\/\/www.synopsys.com\/products\/logic\/design_compiler.html"},{"key":"7_CR25","unstructured":"Samsung Electronics Corporation, http:\/\/www.samsung.com\/products\/semiconductor\/ASIC\/StandardCellLibraries\/STDH150E\/STDH150E.htm"},{"key":"7_CR26","unstructured":"Choi, W., Park, S., Dubois, M.: Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors,\u201d Technical Report #CENG-2007-3, Depart\u00acment of Electrical Engineering - Systems, University of Southern California (March 2007)"}],"container-title":["Lecture Notes in Computer Science","Transactions on High-Performance Embedded Architectures and Compilers II"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-00904-4_7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,19]],"date-time":"2019-05-19T11:58:48Z","timestamp":1558267128000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-00904-4_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783642009037","9783642009044"],"references-count":26,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-00904-4_7","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}