{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,11]],"date-time":"2025-02-11T02:10:02Z","timestamp":1739239802234,"version":"3.37.0"},"publisher-location":"Berlin, Heidelberg","reference-count":37,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642031373"},{"type":"electronic","value":"9783642031380"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-642-03138-0_29","type":"book-chapter","created":{"date-parts":[[2009,7,15]],"date-time":"2009-07-15T09:20:29Z","timestamp":1247649629000},"page":"263-274","source":"Crossref","is-referenced-by-count":8,"title":["Reconfigurable Multithreading Architectures: A Survey"],"prefix":"10.1007","author":[{"given":"Pavel G.","family":"Zaykov","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georgi K.","family":"Kuzmanov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georgi N.","family":"Gaydadjiev","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"29_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"275","DOI":"10.1007\/3-540-44687-7_29","volume-title":"Field-Programmable Logic and Applications","author":"S. Vassiliadis","year":"2001","unstructured":"Vassiliadis, S., Wong, S., Cotofana, S.D.: The MOLEN \u03bc\u03c1-coded processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol.\u00a02147, pp. 275\u2013285. Springer, Heidelberg (2001)"},{"key":"29_CR2","unstructured":"Heysters, P.M.: Coarse-grained reconfigurable computing for power aware applications. In: ERSA, pp. 272\u2013280 (2006)"},{"key":"29_CR3","unstructured":"Seno, K., Yamazaki, M.: Virtual mobile engine (VME) LSI that \u201cchanges its spots\u201d achievies ultralow power and diverse functionality. CX-News\u00a042 (2005), http:\/\/www.sony.com"},{"issue":"1","key":"29_CR4","doi-asserted-by":"publisher","first-page":"29","DOI":"10.1145\/641865.641867","volume":"35","author":"T. Ungerer","year":"2003","unstructured":"Ungerer, T., Robic, B., Silc, J.: A survey of processors with expliclicit multithreading. ACM Computing Surveys\u00a035(1), 29\u201363 (2003)","journal-title":"ACM Computing Surveys"},{"key":"29_CR5","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"79","DOI":"10.1007\/3-540-46117-5_10","volume-title":"Field-Programmable Logic and Applications. Reconfigurable Computing Is Going Mainstream","author":"M. Sima","year":"2002","unstructured":"Sima, M., Vassiliadis, S., Cotofana, S.D., van Eijndhoven, J.T.J., Vissers, K.A.: Field-programmable custom computing machines - a taxonomy. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol.\u00a02438, pp. 79\u201388. Springer, Heidelberg (2002)"},{"key":"29_CR6","first-page":"129","volume-title":"ACSAC","author":"G.B. Wigley","year":"2000","unstructured":"Wigley, G.B., Kearney, D.A.: The first real operating system for reconfigurable computers. In: ACSAC, pp. 129\u2013136. IEEE Computer Society Press, Los Alamitos (2000)"},{"key":"29_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"26","DOI":"10.1007\/978-3-540-71431-6_3","volume-title":"Reconfigurable Computing: Architectures, Tools and Applications","author":"K. Wu","year":"2007","unstructured":"Wu, K., Kanstein, A., Madsen, J., Berekovic, M.: MT-ADRES: Multithreading on coarse-grained reconfigurable architecture. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds.) ARCS 2007. LNCS, vol.\u00a04419, pp. 26\u201338. Springer, Heidelberg (2007)"},{"key":"29_CR8","first-page":"320","volume-title":"ASAP","author":"S. Mamidi","year":"2007","unstructured":"Mamidi, S., Schulte, M., Iancu, D., Glossner, J.: Architecture support for reconfigurable multithreaded processors in programmable communication systems. In: ASAP, pp. 320\u2013327. IEEE Press, Los Alamitos (2007)"},{"key":"29_CR9","doi-asserted-by":"crossref","unstructured":"Uhrig, S., Maier, S., Kuzmanov, G.K., Ungerer, T.: Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling. In: RAW, pp. 209\u2013217 (2006)","DOI":"10.1109\/IPDPS.2006.1639471"},{"key":"29_CR10","doi-asserted-by":"crossref","unstructured":"Peck, W., Anderson, E., Agron, J., Stevens, J., Baijot, F., Andrews, D.: HTHREADS: a computational model for reconfigurable devices. In: FPL, pp. 885\u2013888 (2006)","DOI":"10.1109\/FPL.2006.311336"},{"key":"29_CR11","doi-asserted-by":"crossref","unstructured":"Compton, K., Hauck, S.: Reconfigurable computing: a survey of systems and software. ACM Computing Surveys\u00a034(2), 171\u2013210 (2002)","DOI":"10.1145\/508352.508353"},{"key":"29_CR12","doi-asserted-by":"crossref","unstructured":"Diessel, O., Wigley, G.B.: Opportunities for operating systems research in reconfigurable computing. In: ACRC (1999)","DOI":"10.1007\/BFb0097942"},{"issue":"2","key":"29_CR13","doi-asserted-by":"publisher","first-page":"1401","DOI":"10.1145\/1331331.1331338","volume":"7","author":"H.K.-H. So","year":"2008","unstructured":"So, H.K.-H., Brodersen, R.: A unified hardware\/software runtime environment for FPGA-based reconfigurable computers using BORPH. ACM Transactions on Embedded Computing Systems\u00a07(2), 1401\u20131407 (2008)","journal-title":"ACM Transactions on Embedded Computing Systems"},{"key":"29_CR14","doi-asserted-by":"crossref","unstructured":"Zhou, B., Qui, W., Peng, C.-L.: An operating system framework for reconfigurable systems. In: CIT, pp. 781\u2013787 (2005)","DOI":"10.1109\/CIT.2005.75"},{"issue":"2","key":"29_CR15","doi-asserted-by":"publisher","first-page":"385","DOI":"10.1145\/993396.993404","volume":"3","author":"J. Noguera","year":"2004","unstructured":"Noguera, J., Badia, R.M.: Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling. Trans. on Embedded Computing Sys.\u00a03(2), 385\u2013406 (2004)","journal-title":"Trans. on Embedded Computing Sys."},{"issue":"1","key":"29_CR16","doi-asserted-by":"crossref","first-page":"107","DOI":"10.1016\/j.vlsi.2004.03.002","volume":"38","author":"T. Marescaux","year":"2004","unstructured":"Marescaux, T., Nollet, V., Mignolet, J.-Y., Bartic, A., Moffat, W., Avasare, P., Coene, P., Verkest, D., Vernalde, S., Lauwereins, R.: Run-time support for heterogeneous multitasking on reconfigurable SoCs. Integration\u00a038(1), 107\u2013130 (2004)","journal-title":"Integration"},{"key":"29_CR17","doi-asserted-by":"crossref","unstructured":"Zaykov, P.G., Kuzmanov, G.K., Gaydadjiev, G.N.: State-of-the-art reconfigurable multithreading architectures. Technical Report - CE-TR-2009-02 (2009)","DOI":"10.1007\/978-3-642-03138-0_29"},{"key":"29_CR18","unstructured":"The convey HC-1 computer, architecture overview (white paper), p. 11 (2008), http:\/\/www.conveycomputer.com"},{"key":"29_CR19","unstructured":"Gibeling, G., Schultz, A., Asanovic, K.: The RAMP architecture & description language. In: WARFP (2006)"},{"key":"29_CR20","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"482","DOI":"10.1007\/3-540-46117-5_51","volume-title":"Field-Programmable Logic and Applications. Reconfigurable Computing Is Going Mainstream","author":"S.D. Haynes","year":"2002","unstructured":"Haynes, S.D., Epsom, H.G., Cooper, R.J., McAlpine, P.L.: UltraSONIC: A reconfigurable architecture for video image processing. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol.\u00a02438, pp. 482\u2013491. Springer, Heidelberg (2002)"},{"key":"29_CR21","doi-asserted-by":"crossref","unstructured":"Satrawala, A., Varadarajan, K., Lie, M., Nandy, S., Narayan, R.: Redefine: Architecture of a soc fabric for runtime composition of computation structures. In: FPL 2007, pp. 558\u2013561 (2007)","DOI":"10.1109\/FPL.2007.4380716"},{"key":"29_CR22","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"193","DOI":"10.1007\/978-3-540-39864-6_16","volume-title":"Advances in Computer Systems Architecture","author":"S. Wallner","year":"2003","unstructured":"Wallner, S.: A reconfigurable multi-threaded architecture model. In: Omondi, A.R., Sedukhin, S.G. (eds.) ACSAC 2003. LNCS, vol.\u00a02823, pp. 193\u2013207. Springer, Heidelberg (2003)"},{"key":"29_CR23","doi-asserted-by":"crossref","unstructured":"Bauer, L., Shafique, M., Kreutz, S., Henkel, J.: Run-time system for an extensible embedded processor with dynamic instruction set. In: DATE, pp. 752\u2013757 (2008)","DOI":"10.1145\/1403375.1403558"},{"key":"29_CR24","doi-asserted-by":"crossref","unstructured":"Steiger, C., Walder, H., Platzner, M.: Heuristics for online scheduling real-time tasks to partially reconfigurable devices. In: FPL, pp. 575\u2013584 (2003)","DOI":"10.1007\/978-3-540-45234-8_56"},{"key":"29_CR25","doi-asserted-by":"crossref","unstructured":"Zhou, X., Wang, Y., Huang, X.-Z., Peng, C.-L.: On-line scheduling of real-time tasks for reconfigurable computing system. In: FPT, pp. 57\u201364 (2006)","DOI":"10.1109\/FPT.2006.270295"},{"key":"29_CR26","doi-asserted-by":"crossref","unstructured":"Angermeier, J., Teich, J.: Heuristics for Scheduling Reconfigurable Devices with Consideration of Reconfiguration Overheads. In: Proceedings 15th Reconfigurable Architectures Workshop, Miami, Florida (2008)","DOI":"10.1109\/IPDPS.2008.4536540"},{"issue":"5","key":"29_CR27","doi-asserted-by":"publisher","first-page":"452","DOI":"10.1109\/MDT.2005.100","volume":"22","author":"J. Resano","year":"2005","unstructured":"Resano, J., Mozos, D., Verkest, D., Catthoor, F.: A reconfiguration manager for dynamically reconfigurable hardware. IEEE Design & Test of Computers\u00a022(5), 452\u2013460 (2005)","journal-title":"IEEE Design & Test of Computers"},{"key":"29_CR28","doi-asserted-by":"crossref","unstructured":"Panainte, E.M.: The Molen compiler for reconfigurable architectures. Ph.D. dissertation, TU Delft (2007)","DOI":"10.1145\/1210268.1210274"},{"key":"29_CR29","doi-asserted-by":"crossref","unstructured":"Li, Z., Hauck, S.: Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. In: FPGA, pp. 187\u2013195 (2002)","DOI":"10.1145\/503048.503076"},{"key":"29_CR30","first-page":"224","volume-title":"RTSS","author":"C. Steiger","year":"2003","unstructured":"Steiger, C., Walder, H., Platzner, M., Thiele, L.: Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: RTSS, pp. 224\u2013235. IEEE Computer Society, Los Alamitos (2003)"},{"key":"29_CR31","unstructured":"Dittmann, F.: Methods to exploit reconfigurable fabrics - making reconfigurable systems mature. Ph.D. dissertation, University of Paderborn (2007)"},{"key":"29_CR32","first-page":"223","volume-title":"FPL","author":"H. Kalte","year":"2005","unstructured":"Kalte, H., Porrmann, M.: Context saving and restoring for multitasking in reconfigurable systems. In: FPL, pp. 223\u2013228. IEEE Press, Los Alamitos (2005)"},{"key":"29_CR33","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"121","DOI":"10.1007\/3-540-44614-1_13","volume-title":"Field-Programmable Logic and Applications. The Roadmap to Reconfigurable Computing","author":"H. Simmler","year":"2000","unstructured":"Simmler, H., Levinson, L.: Multitasking on FPGA coprocessors. In: Gr\u00fcnbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol.\u00a01896, pp. 121\u2013130. Springer, Heidelberg (2000)"},{"issue":"1","key":"29_CR34","doi-asserted-by":"publisher","first-page":"15","DOI":"10.1007\/s11265-006-0017-6","volume":"47","author":"M. Majer","year":"2007","unstructured":"Majer, M., Teich, J., Ahmadinia, A., Bobda, C.: The Erlangen Slot Machine: A dynamically reconfigurable fpga-based computer. VLSI Signal Processing\u00a047(1), 15\u201331 (2007)","journal-title":"VLSI Signal Processing"},{"key":"29_CR35","doi-asserted-by":"crossref","unstructured":"Ahmadinia, A., Bobda, C., Koch, D., Majer, M., Teich, J.: Task scheduling for heterogeneous reconfigurable computers. In: SBCCI, pp. 22\u201327 (2004)","DOI":"10.1145\/1016568.1016582"},{"key":"29_CR36","first-page":"1","volume-title":"IPDPS","author":"Y. Chen","year":"2007","unstructured":"Chen, Y., Chen, S.Y.: Cost-driven hybrid configuration prefetching for partial reconfigurable coprocessor. In: IPDPS, pp. 1\u20138. IEEE Press, Los Alamitos (2007)"},{"issue":"5","key":"29_CR37","doi-asserted-by":"publisher","first-page":"624","DOI":"10.1007\/s11390-005-0624-x","volume":"20","author":"S. Wallner","year":"2005","unstructured":"Wallner, S.: Micro-task processing in heterogeneous reconfigurable systems. J. Comput. Sci. Technol.\u00a020(5), 624\u2013634 (2005)","journal-title":"J. Comput. Sci. Technol."}],"container-title":["Lecture Notes in Computer Science","Embedded Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-03138-0_29","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,11]],"date-time":"2025-02-11T01:43:39Z","timestamp":1739238219000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-03138-0_29"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783642031373","9783642031380"],"references-count":37,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-03138-0_29","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}