{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T12:09:15Z","timestamp":1725538155208},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642042836"},{"type":"electronic","value":"9783642042843"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-642-04284-3_9","type":"book-chapter","created":{"date-parts":[[2009,9,14]],"date-time":"2009-09-14T17:55:48Z","timestamp":1252950948000},"page":"89-101","source":"Crossref","is-referenced-by-count":6,"title":["Modeling Cache Effects at the Transaction Level"],"prefix":"10.1007","author":[{"given":"Ardavan","family":"Pedram","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Craven","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Gerstlauer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"unstructured":"Araki, D., Ito, N., Shinsha, T., Mori, Y.: High speed hardware\/software co-verification with cpu model generator from software code. Technical report, InterDesign Technologies Inc (2006)","key":"9_CR1"},{"issue":"2","key":"9_CR2","doi-asserted-by":"publisher","first-page":"169","DOI":"10.1007\/s11265-005-6648-1","volume":"41","author":"L. Benini","year":"2005","unstructured":"Benini, L., Bertozzi, D., Bogliolo, A., Menichelli, F., Olivieri, M.: MPARM: Exploring the multi-processor SoC design space with SystemC. VLSI Signal Processing\u00a041(2), 169\u2013182 (2005)","journal-title":"VLSI Signal Processing"},{"doi-asserted-by":"crossref","unstructured":"Bouchhima, A., Bacivarov, I., Yousseff, W., Bonaciu, M., Jerraya, A.A.: Using abstract CPU subsystem simulation model for high level HW\/SW architecture exploration. In: ASP-DAC, Shanghai, China (January 2005)","key":"9_CR3","DOI":"10.1145\/1120725.1120769"},{"unstructured":"Dale, M.: SWARM Instruction Set Simulator, http:\/\/www.cl.cam.ac.uk\/~mwd24\/phd\/swarm.html","key":"9_CR4"},{"key":"9_CR5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-1481-7","volume-title":"System Design: A Practical Guide with SpecC","author":"A. Gerstlauer","year":"2001","unstructured":"Gerstlauer, A., D\u00f6mer, R., Peng, J., Gajski, D.D.: System Design: A Practical Guide with SpecC. Kluwer, Dordrecht (2001)"},{"key":"9_CR6","volume-title":"Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems","author":"F. Ghenassia","year":"2006","unstructured":"Ghenassia, F.: Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems. Springer, Heidelberg (2006)"},{"doi-asserted-by":"crossref","unstructured":"Ghosh, S., Martonosi, M., Malik, S.: Cache miss equations: an analytical representation of cache misses. In: ICS, Vienna, Austria (1997)","key":"9_CR7","DOI":"10.1145\/263580.263657"},{"issue":"3","key":"9_CR8","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1356052.1356053","volume":"34","author":"K. Goto","year":"2008","unstructured":"Goto, K., van de Geijn, R.A.: Anatomy of high-performance matrix multiplication. ACM Trans. Math. Softw.\u00a034(3), 1\u201325 (2008)","journal-title":"ACM Trans. Math. Softw."},{"key":"9_CR9","volume-title":"System Design with SystemC","author":"T. Grotker","year":"2002","unstructured":"Grotker, T., Li, S., Martin, G., Swan, S.: System Design with SystemC. Kluwer, Dordrecht (2002)"},{"key":"9_CR10","series-title":"Lecture Notes in Computer Science","volume-title":"Applied Parallel Computing. Large Scale Scientific and Industrial Problems","author":"F.G. Gustavson","year":"1998","unstructured":"Gustavson, F.G., Henriksson, A., Jonsson, I., K\u00e5gstr\u00f6m, B., Ling, P.: Superscalar GEMM-based level 3 BLAS - the on-going evolution of a portable and high-performance library. In: K\u00e5gstr\u00f6m, B., Elmroth, E., Wa\u015bniewski, J., Dongarra, J. (eds.) PARA 1998. LNCS, vol.\u00a01541. Springer, Heidelberg (1998)"},{"key":"9_CR11","volume-title":"Computer Architecture - A Quantitative Approach","author":"J. Hennessy","year":"2003","unstructured":"Hennessy, J., Patterson, D.: Computer Architecture - A Quantitative Approach. Morgan Kaufmann, San Francisco (2003)"},{"unstructured":"Hur, I., Lin, C.: Modeling the cache effects of interprocessor communication. In: PDCS, Cambridge, MA (November 1999)","key":"9_CR12"},{"doi-asserted-by":"crossref","unstructured":"Hwang, Y., Abdi, S., Gajski, D.: Cycle approximate retargettable performance estimation at the transaction level. In: DATE, Munich, Germany (March 2008)","key":"9_CR13","DOI":"10.1109\/DATE.2008.4484651"},{"doi-asserted-by":"crossref","unstructured":"Posadas, H., Adamez, J.A., Villar, E., Blasco, F., Escuder, F.: RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model. Design Automation for Embedded Systems\u00a010(4) (December 2005)","key":"9_CR14","DOI":"10.1007\/s10617-006-9725-1"},{"doi-asserted-by":"crossref","unstructured":"Schirner, G., Gerstlauer, A., D\u00f6mer, R.: Abstract, multifaceted modeling of embedded processors for system level design. In: ASP-DAC, Yokohama, Japan (January 2007)","key":"9_CR15","DOI":"10.1109\/ASPDAC.2007.358016"}],"container-title":["IFIP Advances in Information and Communication Technology","Analysis, Architectures and Modelling of Embedded Systems"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-04284-3_9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,22]],"date-time":"2019-05-22T15:20:02Z","timestamp":1558538402000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-04284-3_9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783642042836","9783642042843"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-04284-3_9","relation":{},"ISSN":["1868-4238","1868-422X"],"issn-type":[{"type":"print","value":"1868-4238"},{"type":"electronic","value":"1868-422X"}],"subject":[],"published":{"date-parts":[[2009]]}}}