{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T14:01:53Z","timestamp":1725544913701},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642118012"},{"type":"electronic","value":"9783642118029"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-3-642-11802-9_20","type":"book-chapter","created":{"date-parts":[[2010,2,5]],"date-time":"2010-02-05T12:47:19Z","timestamp":1265374039000},"page":"156-164","source":"Crossref","is-referenced-by-count":1,"title":["Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop"],"prefix":"10.1007","author":[{"given":"Hossein","family":"Karimiyan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sayed Masoud","family":"Sayedi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hossein","family":"Saidi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"2","key":"20_CR1","doi-asserted-by":"publisher","first-page":"305","DOI":"10.1109\/JPROC.2002.808156","volume":"91","author":"K. Roy","year":"2003","unstructured":"Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE\u00a091(2), 305\u2013327 (2003)","journal-title":"Proceedings of the IEEE"},{"key":"20_CR2","volume-title":"CMOS VLSI Design","author":"N. Weste","year":"2004","unstructured":"Weste, N., Harris, D.: CMOS VLSI Design, 3rd edn. Addison-Wesley, Reading (2004)","edition":"3"},{"key":"20_CR3","unstructured":"ITRS, http:\/\/public.itrs.net"},{"key":"20_CR4","doi-asserted-by":"crossref","unstructured":"Powell, M., Yang, S., Falsafi, B., Roy, K., Vijaykumar, T.N.: Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories. In: Proceedings of International Symposium on Low Power Electronics and Design, pp. 90\u201395 (2000)","DOI":"10.1145\/344166.344526"},{"key":"20_CR5","doi-asserted-by":"crossref","unstructured":"Agarwal, A., Li, H., Roy, K.: DRG-Cache: A Data Retention Gated-Ground Cache for Low Power. In: 39th Design Automation Conference (DAC 2002), p. 473 (2002)","DOI":"10.1145\/513918.514037"},{"key":"20_CR6","doi-asserted-by":"crossref","unstructured":"Kahng, A.B., Muddu, S., Sharma, P.: Impact of Gate-Length Biasing on Threshold-Voltage Selection. In: Proceedings of the 7th international Symposium on Quality Electronic Design (2006)","DOI":"10.1109\/ISQED.2006.72"},{"issue":"5\/6","key":"20_CR7","doi-asserted-by":"publisher","first-page":"567","DOI":"10.1147\/rd.475.0567","volume":"47","author":"V.G. Oklobdzija","year":"2003","unstructured":"Oklobdzija, V.G.: Clocking and Clocked Storage Elements in a Multi-Gigahertz Environment. IBM Journal of Research and Development\u00a047(5\/6), 567\u2013584 (2003)","journal-title":"IBM Journal of Research and Development"},{"issue":"6","key":"20_CR8","doi-asserted-by":"publisher","first-page":"861","DOI":"10.1109\/4.585288","volume":"32","author":"S. Shigematsu","year":"1997","unstructured":"Shigematsu, S., Mutoh, S., Matsuya, Y., Tanabe, Y., Yamada, J.: A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. IEEE J. of Solid-State Circuits\u00a032(6), 861\u2013869 (1997)","journal-title":"IEEE J. of Solid-State Circuits"},{"key":"20_CR9","unstructured":"Kao, J., Chandrakasan, A.: MTCMOS sequential circuits. In: Proceedings of the 27th European Solid-State Circuits Conference, ESSCIRC 2001, September 2001, pp. 317\u2013320 (2001)"},{"issue":"5","key":"20_CR10","doi-asserted-by":"publisher","first-page":"818","DOI":"10.1109\/JSSC.2004.826335","volume":"39","author":"B.H. Calhoun","year":"2004","unstructured":"Calhoun, B.H., Honore, F.A., Chandrakasan, A.P.: A leakage reduction methodology for distributed MTCMOS. IEEE Journal of Solid-State Circuits\u00a039(5), 818\u2013826 (2004)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"20_CR11","doi-asserted-by":"crossref","unstructured":"Vesterbacka, M.: A Robust Differential Scan Flip-Flop. In: Proc. IEEE Int. Symp. on Circuits and Systems, I, pp. 334\u2013337 (1999)","DOI":"10.1109\/ISCAS.1999.777871"},{"issue":"4","key":"20_CR12","doi-asserted-by":"publisher","first-page":"536","DOI":"10.1109\/4.753687","volume":"34","author":"V. Stojanovic","year":"1999","unstructured":"Stojanovic, V., Oklobdzija, V.G.: Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE Journal of Solid-State Circuits\u00a034(4), 536\u2013548 (1999)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"20_CR13","doi-asserted-by":"publisher","DOI":"10.1002\/0470033371","volume-title":"Multi-Voltage CMOS Circuit Design","author":"V. Kursun","year":"2006","unstructured":"Kursun, V., Friedman, E.G.: Multi-Voltage CMOS Circuit Design. John Wiley & Sons Ltd., Chichester (2006)"},{"issue":"4","key":"20_CR14","doi-asserted-by":"publisher","first-page":"867","DOI":"10.1109\/TCSI.2005.860119","volume":"53","author":"S. Goel","year":"2006","unstructured":"Goel, S., Elgamel, M.A., Bayoumi, M.A., Hanafy, Y.: Design methodologies for high-performance noise-tolerant XOR-XNOR circuits. IEEE Transactions on Circuits and Systems I: Regular Papers\u00a053(4), 867\u2013878 (2006)","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"issue":"3","key":"20_CR15","doi-asserted-by":"publisher","first-page":"338","DOI":"10.1109\/TVLSI.2007.893623","volume":"15","author":"P. Zhao","year":"2007","unstructured":"Zhao, P., McNeely, J., Golconda, P., Bayoumi, M.A., Barcenas, R.A., Kuang, W.: Low-power clock branch sharing double-edge triggered flip-flop. IEEE Trans. Very Large Scale Integr. Syst.\u00a015(3), 338\u2013345 (2007)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"issue":"2","key":"20_CR16","doi-asserted-by":"publisher","first-page":"185","DOI":"10.1109\/TVLSI.2003.821548","volume":"12","author":"F. Ishihara","year":"2004","unstructured":"Ishihara, F., Sheikh, F., Nikoli\u0107, B.: Level conversion for dual-supply systems. IEEE Trans. Very Large Scale Integr. Syst.\u00a012(2), 185\u2013195 (2004)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"20_CR17","doi-asserted-by":"crossref","unstructured":"Tschanz, J., Narendra, S., Chen, Z., Borkar, S., Sachdev, M., De, V.: Comparative Delay and Energy of Single Edge-triggered and Dual Edge Triggered Pulsed Flip-flops for High-performance Microprocessors. In: Proc. ISPLED 2001, pp. 207\u2013212 (2001)","DOI":"10.1145\/383082.383121"},{"key":"20_CR18","doi-asserted-by":"crossref","unstructured":"Nedovic, N., Oklobdzija, V.G.: Dual-edge triggered storage elements and clocking strategy for low-power systems. IEEE Trans. Very Large Scale Integr. Syst.\u00a013(5) (May 2005)","DOI":"10.1109\/TVLSI.2005.844302"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-11802-9_20","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,25]],"date-time":"2019-05-25T16:24:14Z","timestamp":1558801454000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-11802-9_20"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"ISBN":["9783642118012","9783642118029"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-11802-9_20","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2010]]}}}