{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,29]],"date-time":"2025-12-29T22:06:06Z","timestamp":1767045966398},"publisher-location":"Berlin, Heidelberg","reference-count":8,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642118012"},{"type":"electronic","value":"9783642118029"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-3-642-11802-9_27","type":"book-chapter","created":{"date-parts":[[2010,2,5]],"date-time":"2010-02-05T12:47:19Z","timestamp":1265374039000},"page":"227-236","source":"Crossref","is-referenced-by-count":1,"title":["Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering"],"prefix":"10.1007","author":[{"given":"Gaurang","family":"Upasani","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrea","family":"Calimera","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alberto","family":"Macii","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Enrico","family":"Macii","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Massimo","family":"Poncino","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"2","key":"27_CR1","doi-asserted-by":"publisher","first-page":"305","DOI":"10.1109\/JPROC.2002.808156","volume":"91","author":"K. Roy","year":"2003","unstructured":"Roy, K., Mukhopadhyay, S., Mahmoodi Meimand, H.: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proceedings of the IEEE\u00a091(2), 305\u2013327 (2003)","journal-title":"Proceedings of the IEEE"},{"issue":"1","key":"27_CR2","doi-asserted-by":"publisher","first-page":"6","DOI":"10.1109\/7384.928306","volume":"1","author":"L. Benini","year":"2001","unstructured":"Benini, L., De Micheli, G., Macii, E.: Designing Low-Power Circuits: Practical Recipes. IEEE Circuits and Systems Magazine\u00a01(1), 6\u201325 (2001)","journal-title":"IEEE Circuits and Systems Magazine"},{"issue":"4","key":"27_CR3","doi-asserted-by":"publisher","first-page":"32","DOI":"10.1109\/54.329451","volume":"11","author":"L. Benini","year":"1994","unstructured":"Benini, L., Siegel, P., De Micheli, G.: Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits. IEEE Design and Test of Computers\u00a011(4), 32\u201340 (1994)","journal-title":"IEEE Design and Test of Computers"},{"issue":"10","key":"27_CR4","doi-asserted-by":"crossref","first-page":"1324","DOI":"10.1109\/TCAD.2003.818127","volume":"22","author":"M. Anis","year":"2003","unstructured":"Anis, M., Areibi, S., Elmasry, M.: Design and Optimization of Multi-Threshold CMOS Circuits. IEEE Tran. on CAD\u00a022(10), 1324\u20131342 (2003)","journal-title":"IEEE Tran. on CAD"},{"doi-asserted-by":"crossref","unstructured":"Sathanur, A., Pullini, A., Benini, L., Macii, A., Macii, E., Poncino, M.: Timing-Driven Row-Based Power Gating. In: ISLPED 2007: ACM\/IEEE Intl. Symp. on Low Power Electronics and Design, Portland, OR, pp. 104\u2013109 (2007)","key":"27_CR5","DOI":"10.1145\/1283780.1283803"},{"doi-asserted-by":"crossref","unstructured":"Bolzani, L., Calimera, A., Macii, A., Macii, E., Poncino, M.: Enabling Concurrent Clock and Power Gating in an Industrial Design Flow. In: DATE 2009: IEEE Design Automation and Test in Europe, Nice, pp. 334\u2013339 (2009)","key":"27_CR6","DOI":"10.1109\/DATE.2009.5090684"},{"doi-asserted-by":"crossref","unstructured":"Bolzani, L., Calimera, A., Macii, A., Macii, E., Poncino, M.: Placement-aware clustering for integrated clock and power gating. In: ISCAS 2009: IEEE Intl. Symp. on Circuits and Systems, Taipei, pp. 1723\u20131726 (2009)","key":"27_CR7","DOI":"10.1109\/ISCAS.2009.5118107"},{"key":"27_CR8","doi-asserted-by":"crossref","first-page":"291","DOI":"10.1002\/j.1538-7305.1970.tb01770.x","volume":"49","author":"W.B. Kernighan","year":"1970","unstructured":"Kernighan, W.B., Lin, S.: Efficient Heuristic Procedure for Partitioning Graphs. Bell System Tech. Journal\u00a049, 291\u2013307 (1970)","journal-title":"Bell System Tech. Journal"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-11802-9_27","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,3,12]],"date-time":"2019-03-12T05:27:21Z","timestamp":1552368441000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-11802-9_27"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"ISBN":["9783642118012","9783642118029"],"references-count":8,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-11802-9_27","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2010]]}}}