{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:59:41Z","timestamp":1725551981345},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642119491"},{"type":"electronic","value":"9783642119507"}],"license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-3-642-11950-7_13","type":"book-chapter","created":{"date-parts":[[2010,4,7]],"date-time":"2010-04-07T10:00:27Z","timestamp":1270634427000},"page":"138-149","source":"Crossref","is-referenced-by-count":2,"title":["Efficient Transaction Nesting in Hardware Transactional Memory"],"prefix":"10.1007","author":[{"given":"Yi","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yangming","family":"Su","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cui","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mingyu","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xin","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"He","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Depei","family":"Qian","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"13_CR1","doi-asserted-by":"publisher","first-page":"289","DOI":"10.1109\/ISCA.1993.698569","volume-title":"20th International Symposium on Computer Architecture","author":"M. Herlihy","year":"1993","unstructured":"Herlihy, M., Eliot, J., Moss, B.: Transactional memory: Architectural support for lock-free data structures. In: 20th International Symposium on Computer Architecture, pp. 289\u2013300. IEEE Computer Society, San Diego (1993)"},{"key":"13_CR2","doi-asserted-by":"publisher","first-page":"102","DOI":"10.1109\/ISCA.2004.1310767","volume-title":"31st International Symposium on Computer Architecture","author":"L. Hammond","year":"2004","unstructured":"Hammond, L., Wong, V., Chen, M.: Transactional memory coherence and consistency. In: 31st International Symposium on Computer Architecture, pp. 102\u2013113. IEEE Computer Society, Munich (2004)"},{"issue":"1","key":"13_CR3","doi-asserted-by":"publisher","first-page":"59","DOI":"10.1109\/MM.2006.26","volume":"26","author":"C. Scott Ananian","year":"2006","unstructured":"Scott Ananian, C., Asanovic, K., Kuszmaul, B.C.: Unbounded transactional memory. IEEE Micro\u00a026(1), 59\u201369 (2006)","journal-title":"IEEE Micro"},{"key":"13_CR4","first-page":"258","volume-title":"12th International Symposium on High-Performance Computer Architecture","author":"K.E. Moore","year":"2006","unstructured":"Moore, K.E., Bobba, J., Moravan, M.J.: LogTM: log-based transactional memory. In: 12th International Symposium on High-Performance Computer Architecture, pp. 258\u2013269. IEEE Computer Society, Austin (2006)"},{"key":"13_CR5","doi-asserted-by":"crossref","first-page":"127","DOI":"10.1109\/ISCA.2008.24","volume-title":"35th International Symposium on Computer Architecture (ISCA 2008)","author":"J. Bobba","year":"2008","unstructured":"Bobba, J., Goyal, N., Hill, M.D.: TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory. In: 35th International Symposium on Computer Architecture (ISCA 2008), pp. 127\u2013138. IEEE Computer Society, Beijing (2008)"},{"key":"13_CR6","first-page":"204","volume-title":"14th annual ACM symposium on Principles of distributed computing","author":"N. Shavit","year":"1995","unstructured":"Shavit, N., Touitou, D.: Software transactional memory. In: 14th annual ACM symposium on Principles of distributed computing, pp. 204\u2013213. ACM Press, Ottawa (1995)"},{"key":"13_CR7","first-page":"187","volume-title":"11th ACM SIGPLAN symposium on Principles and practice of parallel programming","author":"B. Saha","year":"2006","unstructured":"Saha, B., Adl-Tabatabai, A.-R., Hudson, R.L.: McRT-STM: a high performance software transactional memory system for a multi-core runtime. In: 11th ACM SIGPLAN symposium on Principles and practice of parallel programming, pp. 187\u2013197. ACM, New York (2006)"},{"issue":"5","key":"13_CR8","doi-asserted-by":"publisher","first-page":"5","DOI":"10.1145\/635508.605399","volume":"36","author":"Rajwar","year":"2002","unstructured":"Rajwar, Ravi, Goodman, James, R.: Transactional lock-free execution of lock-based programs. ACM Operating Systems Review\u00a036(5), 5\u201317 (2002)","journal-title":"ACM Operating Systems Review"},{"key":"13_CR9","doi-asserted-by":"publisher","first-page":"26","DOI":"10.1145\/1133981.1133985","volume-title":"2006 ACM SIGPLAN conference on Programming language design and implementation","author":"A.-R. Adl-Tabatabai","year":"2006","unstructured":"Adl-Tabatabai, A.-R., Lewis, B.T., Menon, V.: Compiler and runtime support for efficient software transactional memory. In: 2006 ACM SIGPLAN conference on Programming language design and implementation, pp. 26\u201337. ACM, Ottawa (2006)"},{"key":"13_CR10","doi-asserted-by":"publisher","first-page":"48","DOI":"10.1145\/1065944.1065952","volume-title":"2005 ACM SIGPLAN Symposium on Principles and Practise of Parallel Programming","author":"T. Harris","year":"2005","unstructured":"Harris, T., Marlow, S., Jones, S.P.: Composable memory transactions. In: 2005 ACM SIGPLAN Symposium on Principles and Practise of Parallel Programming, pp. 48\u201360. ACM, Chicago (2005)"},{"key":"13_CR11","first-page":"494","volume-title":"32nd International Symposium on Computer Architecture","author":"R. Rajwar","year":"2005","unstructured":"Rajwar, R., Herlihy, M., Lai, K.: Virtualizing transactional memory. In: 32nd International Symposium on Computer Architecture, pp. 494\u2013505. IEEE Computer Society, Madison (2005)"},{"key":"13_CR12","first-page":"209","volume-title":"11th ACM SIGPLAN symposium on Principles and practice of parallel programming","author":"S. Kumar","year":"2006","unstructured":"Kumar, S., Chu, M., Hughes, C.J.: Hybrid transactional memory. In: 11th ACM SIGPLAN symposium on Principles and practice of parallel programming, pp. 209\u2013220. ACM, New York (2006)"},{"issue":"1","key":"13_CR13","doi-asserted-by":"publisher","first-page":"67","DOI":"10.1109\/MM.2007.26","volume":"27","author":"A. McDonald","year":"2007","unstructured":"McDonald, A., Carlstrom, B., Chung, J.W.: Transactional memory: The hardware-software interface. IEEE Micro\u00a027(1), 67\u201376 (2007)","journal-title":"IEEE Micro"},{"key":"13_CR14","doi-asserted-by":"crossref","first-page":"115","DOI":"10.1109\/ISCA.2008.34","volume-title":"35th International Symposium on Computer Architecture (ISCA 2008)","author":"L. Baugh","year":"2008","unstructured":"Baugh, L., Neelakantam, N., Zilles, C.: Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory. In: 35th International Symposium on Computer Architecture (ISCA 2008), pp. 115\u2013126. IEEE Computer Society, Beijing (2008)"},{"issue":"3","key":"13_CR15","doi-asserted-by":"publisher","first-page":"8","DOI":"10.1109\/MM.2007.63","volume":"27","author":"T. Harris","year":"2007","unstructured":"Harris, T., Cristal, A., Unsal, O.: Transactional memory: An overview. IEEE Micro\u00a027(3), 8\u201320 (2007)","journal-title":"IEEE Micro"},{"key":"13_CR16","doi-asserted-by":"crossref","unstructured":"Moravan, M.J., Bobba, J., Moore, K.E.: Supporting Nested Transactional Memory in LogTM. In: 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) (October 2006)","DOI":"10.1145\/1168857.1168902"},{"key":"13_CR17","doi-asserted-by":"crossref","unstructured":"Magnusson, P.S.: Simics: A Full System Simulation Platform. IEEE Computer (February 2002)","DOI":"10.1109\/2.982916"},{"key":"13_CR18","doi-asserted-by":"crossref","unstructured":"Martin, M.M.K., Sorin, D.J., Beckmann, B.M.: Multifacet\u2019s General Execution-driven Multiprocessor Simulator (GEMS) Toolset. Computer Architecture News, CAN (September 2005)","DOI":"10.1145\/1105734.1105747"}],"container-title":["Lecture Notes in Computer Science","Architecture of Computing Systems - ARCS 2010"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-11950-7_13","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,19]],"date-time":"2019-05-19T17:56:50Z","timestamp":1558288610000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-11950-7_13"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"ISBN":["9783642119491","9783642119507"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-11950-7_13","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2010]]}}}