{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:35:33Z","timestamp":1761647733961,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642121326"},{"type":"electronic","value":"9783642121333"}],"license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-3-642-12133-3_16","type":"book-chapter","created":{"date-parts":[[2010,3,8]],"date-time":"2010-03-08T10:25:50Z","timestamp":1268043950000},"page":"157-168","source":"Crossref","is-referenced-by-count":11,"title":["A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs"],"prefix":"10.1007","author":[{"given":"Antonio","family":"Roldao Lopes","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"George A.","family":"Constantinides","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"16_CR1","doi-asserted-by":"crossref","unstructured":"Boland, D., Constantinides, G.: An FPGA-based Implementation of the MINRES algorithm. In: Proc. of Field Programmable Logic, pp. 379\u2013384 (2008)","DOI":"10.1109\/FPL.2008.4629967"},{"key":"16_CR2","doi-asserted-by":"crossref","unstructured":"Junaid, K., Ravindrann, G.: FPGA Accelerator For Medical Image Compression System. In: Proc. of International Conference on Biomedical Engineering, pp. 396\u2013399 (2006)","DOI":"10.1007\/978-3-540-68017-8_100"},{"key":"16_CR3","unstructured":"IEEE, 754 Standard for Binary Floating-Point Arithmetic (1985), http:\/\/grouper.ieee.org\/groups\/754\/ (accessed on 25\/10\/2009)"},{"key":"16_CR4","doi-asserted-by":"crossref","unstructured":"Langhammer, M.: Floating point datapath synthesis for FPGAs. In: Proc. of Field Programmable Logic and Applications, pp. 355\u2013360 (2008)","DOI":"10.1109\/FPL.2008.4629963"},{"key":"16_CR5","unstructured":"Roldao, A., Constantinides, G.: High Throughput FPGA-based Floating Point Conjugate Gradient Implementation. In: Proc. of Applied Reconfigurable Computing, pp. 75\u201386 (2008)"},{"key":"16_CR6","doi-asserted-by":"crossref","unstructured":"Underwood, K., Hemmert, S.: Closing the gap: CPU and FPGA Trends in sustainable floating-point BLAS Performance. In: Proc. of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 219\u2013228 (2004)","DOI":"10.1109\/FCCM.2004.21"},{"key":"16_CR7","doi-asserted-by":"publisher","first-page":"1377","DOI":"10.1109\/TPDS.2007.1068","volume":"18","author":"L. Zhuo","year":"2007","unstructured":"Zhuo, L., Morris, G., Prasanna, V.: High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs. IEEE Transactions on Parallel and Distributed Systems\u00a018, 1377\u20131392 (2007)","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"16_CR8","doi-asserted-by":"crossref","unstructured":"Saleh, H., Swartzlander, E.: A Floating-point Fused Dot-product Unit. In: Proc. of IEEE International Conference on Computer Design, pp. 427\u2013431 (2008)","DOI":"10.1109\/ICCD.2008.4751896"},{"key":"16_CR9","unstructured":"Dinechin, F.: FloPoCo is a generator of arithmetic cores (Floating-Point Cores), http:\/\/www.ens-lyon.fr\/LIP\/Arenaire\/Ware\/FloPoCo\/ (accessed on 19\/10\/2009)"},{"key":"16_CR10","unstructured":"Collaborative Project, Multi-precision Floating Point Library, http:\/\/www.mpfr.org\/ (accessed on 02\/01\/2009)"}],"container-title":["Lecture Notes in Computer Science","Reconfigurable Computing: Architectures, Tools and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-12133-3_16","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,19]],"date-time":"2025-02-19T01:50:05Z","timestamp":1739929805000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-642-12133-3_16"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"ISBN":["9783642121326","9783642121333"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-12133-3_16","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2010]]}}}