{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,13]],"date-time":"2026-05-13T17:21:34Z","timestamp":1778692894222,"version":"3.51.4"},"publisher-location":"Berlin, Heidelberg","reference-count":7,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783642122132","type":"print"},{"value":"9783642122149","type":"electronic"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-3-642-12214-9_20","type":"book-chapter","created":{"date-parts":[[2010,3,31]],"date-time":"2010-03-31T15:11:44Z","timestamp":1270048304000},"page":"114-119","source":"Crossref","is-referenced-by-count":1,"title":["Power Consumption Analysis of Direct, Set Associative and Phased Set Associative Cache Organizations in Alpha AXP 21064 Processor"],"prefix":"10.1007","author":[{"given":"Megalingam Rajesh","family":"Kannan","sequence":"first","affiliation":[]},{"given":"K. B.","family":"Deepu","sequence":"additional","affiliation":[]},{"given":"Joseph P.","family":"Iype","sequence":"additional","affiliation":[]},{"given":"Ravishankar","family":"Parthasarathy","sequence":"additional","affiliation":[]},{"given":"Popuri","family":"Gautham","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"20_CR1","doi-asserted-by":"crossref","unstructured":"Calder, B., Grunwald, D., Emer, J.: Predictive Sequential Associative Cache. In: Proceedings of Second International Symposium on High-Performance Computer Architecture, February 1996, pp. 244\u2013253 (1996)","DOI":"10.1109\/HPCA.1996.501190"},{"key":"20_CR2","doi-asserted-by":"crossref","unstructured":"Chang, J.H., Chao, H., So, K.: Cache design of a sub-micron cmos system\/370. In: 14th Annual International Symposium on Computer Architecture, SIGARCH Newsletter, June 1987, pp. 208\u2013213 (1987)","DOI":"10.1145\/30350.30374"},{"key":"20_CR3","unstructured":"Koji, I., Tohru, I., Kazuaki, M.: Way Predicting Set Associative Cache for High Performance and Low Energy Consumption. In: ISLPED 1999, San Diego, CA, USA (1999)"},{"issue":"6","key":"20_CR4","doi-asserted-by":"publisher","first-page":"11","DOI":"10.1109\/40.476254","volume":"15","author":"A. Hasegawa","year":"1995","unstructured":"Hasegawa, A., et al.: SH3: High Code Density, Low Power. IEEE Micro\u00a015(6), 11\u201319 (1995)","journal-title":"IEEE Micro"},{"key":"20_CR5","doi-asserted-by":"crossref","unstructured":"Megalingam, R.K., Deepu, K.B., Joseph, I.P., Vikram, V.: Phased Set Associative Cache Design For Reduced Power Consumption. In: 2nd IEEE ICCSIT 2009, Beijing, China (2009)","DOI":"10.1109\/ICCSIT.2009.5234663"},{"key":"20_CR6","doi-asserted-by":"crossref","unstructured":"Kin, J., Gupta, M., Mangione-Smith, W.H.: The Filter Cache: An Energy Efficient Memory Structure. In: IEEE\/ACM International Symposium on Microarchitecture (MICRO-30), pp. 184\u2013193 (1997)","DOI":"10.1109\/MICRO.1997.645809"},{"key":"20_CR7","unstructured":"Patterson, D.A., Hennesy, J.L.: Computer Organization and Design, 2nd edn."}],"container-title":["Communications in Computer and Information Science","Information Processing and Management"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-12214-9_20.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,23]],"date-time":"2020-11-23T21:51:37Z","timestamp":1606168297000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-12214-9_20"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"ISBN":["9783642122132","9783642122149"],"references-count":7,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-12214-9_20","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"value":"1865-0929","type":"print"},{"value":"1865-0937","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010]]}}}