{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,22]],"date-time":"2025-02-22T05:08:52Z","timestamp":1740200932071,"version":"3.37.3"},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642131356"},{"type":"electronic","value":"9783642131363"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-3-642-13136-3_44","type":"book-chapter","created":{"date-parts":[[2010,5,25]],"date-time":"2010-05-25T22:20:16Z","timestamp":1274826016000},"page":"434-443","source":"Crossref","is-referenced-by-count":0,"title":["Test Data Compression Using Four-Coded and Sparse Storage for Testing Embedded Core"],"prefix":"10.1007","author":[{"given":"Zhang","family":"Ling","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kuang","family":"Ji-shun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"You","family":"zhi-qiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"44_CR1","doi-asserted-by":"publisher","first-page":"719","DOI":"10.1109\/TVLSI.2005.844311","volume":"13","author":"M. Tehranipoor","year":"2005","unstructured":"Tehranipoor, M., Nourani, M., Chakrabarty, K.: Nine-Coded Compression Technique for Testing Embedded Cores in SoCs. IEEE transactions on very large scale integration(VLSI) systems\u00a013, 719\u2013731 (2005)","journal-title":"IEEE transactions on very large scale integration(VLSI) systems"},{"key":"44_CR2","doi-asserted-by":"crossref","unstructured":"Hsu, F., Butler, K., Patel, J.: A case study on the implementation of the Illinois scan architecture. In: Proc. Int. Test Conf (ITC\u201901), pp. 538\u2013547 (2001)","DOI":"10.1109\/TEST.2001.966672"},{"key":"44_CR3","doi-asserted-by":"crossref","unstructured":"Wang, L.-T., Wang, Z., wen, X., et al.: VirtualScan: Test Compression Technology Using Combinatioal Logic and One-Pass ATPG. IEEE Design & Test of Computers, 122\u2013129 (2008)","DOI":"10.1109\/MDT.2008.56"},{"issue":"5","key":"44_CR4","doi-asserted-by":"publisher","first-page":"776","DOI":"10.1109\/TCAD.2004.826558","volume":"23","author":"J. Rajski","year":"2004","unstructured":"Rajski, J., Tyszer, J., Kassab, M., Mukherjee, N.: Embedded Deterministic test. IEEE transactions on computer-aided design of integrated circuits and systems\u00a023(5), 776\u2013792 (2004)","journal-title":"IEEE transactions on computer-aided design of integrated circuits and systems"},{"issue":"3","key":"44_CR5","doi-asserted-by":"publisher","first-page":"352","DOI":"10.1109\/TCAD.2002.807895","volume":"22","author":"A. Chandra","year":"2003","unstructured":"Chandra, A., Chandrabarty, A.: A Unified Approach to Reduce SOC Test Data Volum, Scan Power and Testing Time. IEEE Transactions on Computer-aided design of integrated circuits and system\u00a022(3), 352\u2013362 (2003)","journal-title":"IEEE Transactions on Computer-aided design of integrated circuits and system"},{"key":"44_CR6","doi-asserted-by":"publisher","first-page":"355","DOI":"10.1109\/43.913754","volume":"20","author":"A. Chandra","year":"2001","unstructured":"Chandra, A., Chakrabarty, K.: System-on-a-chip Test-data Compression and Decompression Integrated Circuits and Systems. IEEE transaction on computer-Aided design of integrated circuits and systems\u00a020, 355\u2013368 (2001)","journal-title":"IEEE transaction on computer-Aided design of integrated circuits and systems"},{"key":"44_CR7","doi-asserted-by":"crossref","unstructured":"Chandra, A., Chakrabarty, K.: Frequency-diredted Run-length(FDR) Codes with Application to System-on-a-Chip Test Data Compression. In: Proceedings of 19th IEEE VLSI Test Symposium (VTS 2001), pp. 42\u201347 (2001)","DOI":"10.1109\/VTS.2001.923416"},{"key":"44_CR8","doi-asserted-by":"crossref","unstructured":"EL-Maleh, A.H.: Test data compression for system-on-a-chip using extended Frequency-Directed Run-Length Code. IET Computers & Digital Techniques, 155\u2013163 (2008)","DOI":"10.1049\/iet-cdt:20070028"},{"key":"44_CR9","doi-asserted-by":"crossref","unstructured":"Nourani, M., Tehranipour, M.: RL-Huffman encoding for test compression and power reduction in scan applicaiton. ACM trans. Des. AUTOM. Electron. Syst., 91\u2013115 (2005)","DOI":"10.1145\/1044111.1044117"},{"key":"44_CR10","doi-asserted-by":"crossref","unstructured":"Jas, A., Gosh-Dastidar, J., Ng, M., Touba, N.: An effcient test vector compression scheme using selective Huffman coding. IEEE Trans. Comput. Aided Des., 797\u2013806 (2003)","DOI":"10.1109\/TCAD.2003.811452"},{"key":"44_CR11","first-page":"1290","volume-title":"Reseeding using Compaction of Pre-Generated LFSR Sub-Sequences","author":"A. Jutman","year":"2008","unstructured":"Jutman, A., Alekejev, I., Raik, J., et al.: Reseeding using Compaction of Pre-Generated LFSR Sub-Sequences, pp. 1290\u20131295. IEEE, Los Alamitos (2008)"},{"key":"44_CR12","doi-asserted-by":"crossref","unstructured":"Knieser, M., Wolff, F., Papachristou, C., Wyer, D., McIntyre, D.: A technique for high ratio LZW compression. In: Proc. Design Automation Test in Europe, pp. 116\u2013121 (2003)","DOI":"10.1109\/DATE.2003.1253596"},{"key":"44_CR13","doi-asserted-by":"crossref","unstructured":"Hiraide, T., Boateng, K., Konishi, H., Itaya, K., Emori, M., Yamanaka, H.: BIST-aided scan test\u2014A new method for test cost reduction. In: Proc. VLSI Test Symp. (VTS\u201903), pp. 359\u2013364 (2003)","DOI":"10.1109\/VTEST.2003.1197675"},{"key":"44_CR14","doi-asserted-by":"crossref","unstructured":"Hamzaoglu, I., Patel, J.H.: Test set compaction algorithms for combinational circuits. In: Proc. Int. Conf. Computer-Aided Design, pp. 283\u2013289 (1998)","DOI":"10.1145\/288548.288615"},{"key":"44_CR15","doi-asserted-by":"crossref","unstructured":"EL-Maleh, A.H.: Efficient test compression technique based on block merging. IET compter& Digital Techniques, 327\u2013335 (2007)","DOI":"10.1049\/iet-cdt:20070003"}],"container-title":["Lecture Notes in Computer Science","Algorithms and Architectures for Parallel Processing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-13136-3_44.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T04:12:53Z","timestamp":1740111173000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-13136-3_44"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"ISBN":["9783642131356","9783642131363"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-13136-3_44","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2010]]}}}