{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,23]],"date-time":"2025-07-23T12:18:01Z","timestamp":1753273081164,"version":"3.37.3"},"publisher-location":"Berlin, Heidelberg","reference-count":27,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642147050"},{"type":"electronic","value":"9783642147067"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-3-642-14706-7_6","type":"book-chapter","created":{"date-parts":[[2010,8,11]],"date-time":"2010-08-11T09:14:43Z","timestamp":1281518083000},"page":"70-85","source":"Crossref","is-referenced-by-count":7,"title":["A Predictive Model for Cache-Based Side Channels in Multicore and Multithreaded Microprocessors"],"prefix":"10.1007","author":[{"given":"Leonid","family":"Domnitser","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nael","family":"Abu-Ghazaleh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dmitry","family":"Ponomarev","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"unstructured":"Bernstein, D.: Cache-timing attacks on aes (2005), http:\/\/cr.yp.to\/antiforgery\/cachetiming-20050414.pdf","key":"6_CR1"},{"unstructured":"The blowfish encryption algorithm (2009), http:\/\/www.schneier.com\/blowfish.html","key":"6_CR2"},{"key":"6_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"201","DOI":"10.1007\/11894063_16","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2006","author":"J. Bonneau","year":"2006","unstructured":"Bonneau, J., Mironov, I.: Cache-collision timing attacks against aes. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol.\u00a04249, pp. 201\u2013215. Springer, Heidelberg (2006)"},{"unstructured":"Brickell, E., Graunke, G., Neve, M., Seifert, J.: Software mitigation to hedge aes against cache-based software side channel vulnerabilities. In: IACR ePrint Archive, Report 2006\/052 (2006)","key":"6_CR4"},{"unstructured":"Canteaut, A., Lauradoux, C., Seznec, A.: Understanding cache attacks. INRIA Technical Report (2006), ftp:\/\/ftp.inria.fr\/INRIA\/publication\/publi-pdf\/RR\/RR-5881.pdf","key":"6_CR5"},{"key":"6_CR6","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-662-04722-4","volume-title":"The design of rijndael: Aes - the advanced encryption standard","author":"J. Daemen","year":"2002","unstructured":"Daemen, J., Rijmen, V.: The design of rijndael: Aes - the advanced encryption standard. Springer, Heidelberg (2002)"},{"doi-asserted-by":"crossref","unstructured":"Burger, D., Austin, T.: The simplescalar toolset: Version 2.0 (June 1997)","key":"6_CR7","DOI":"10.1145\/268806.268810"},{"unstructured":"Page, D.: Partitioned cache architecture as a side-channel defense mechanism. In: Cryptography ePrint Archive (2005)","key":"6_CR8"},{"issue":"1","key":"6_CR9","doi-asserted-by":"publisher","first-page":"3","DOI":"10.1007\/BF00630563","volume":"4","author":"E. Biham","year":"1991","unstructured":"Biham, E., Shamir, A.: Packaging of multi-core microprocessors: Tradeoffs and potential solutions. Journal of Cryptology\u00a04(1), 3\u201372 (1991)","journal-title":"Journal of Cryptology"},{"unstructured":"Goubin, L., Patarin, J.: DES and differential power analysis. In: Proc. of CHES (1999)","key":"6_CR10"},{"unstructured":"Gueron, S.: Advanced encryption standard (aes) instruction set (2008)","key":"6_CR11"},{"doi-asserted-by":"crossref","unstructured":"Kong, J., Aclicmez, O., Seifert, J., Zhou, H.: Hardware-software integrated approaches to defend against software cache-based side channel attacks. In: International Symposium on High Performance Computer Architecture (HPCA) (February 2009)","key":"6_CR12","DOI":"10.1109\/HPCA.2009.4798277"},{"doi-asserted-by":"crossref","unstructured":"Kopf, B., Basin, D.: An information-theoretic model for adaptive side-channel attacks. In: ACM Conference on Computer and Communication Security (CCS), pp. 286\u2013296 (2007)","key":"6_CR13","DOI":"10.1145\/1315245.1315282"},{"key":"6_CR14","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"386","DOI":"10.1007\/3-540-48285-7_33","volume-title":"Advances in Cryptology - EUROCRYPT \u201993","author":"M. Matsui","year":"1994","unstructured":"Matsui, M.: Linear cryptanalysis method for des cipher. In: Helleseth, T. (ed.) EUROCRYPT 1993. LNCS, vol.\u00a0765, pp. 386\u2013397. Springer, Heidelberg (1994)"},{"doi-asserted-by":"crossref","unstructured":"May, D., Muller, H., Smart, N.: Randomized register renaming to foil DPA. In: Proc. of CHES (2001)","key":"6_CR15","DOI":"10.1007\/3-540-44709-1_4"},{"doi-asserted-by":"crossref","unstructured":"Micali, S., Reyzin, L.: Physically observable cryptography. In: Proc. of Theory of Cryptography Conference (2004)","key":"6_CR16","DOI":"10.1007\/978-3-540-24638-1_16"},{"unstructured":"M-sim version 3.0, code and documentation (2005), http:\/\/www.cs.binghamton.edu\/~msim","key":"6_CR17"},{"doi-asserted-by":"crossref","unstructured":"Osvik, D., Shamir, A., Tromer, E.: Cache attacks and countermeasures: the case of aes. In: Cryptology ePrint Archive, Report 2005\/271 (2005)","key":"6_CR18","DOI":"10.1007\/11605805_1"},{"unstructured":"Percival, C.: Cache missing for fun and profit (2005), http:\/\/www.daemonology.net\/papers\/htt.pdf","key":"6_CR19"},{"unstructured":"Random.org (2009), http:\/\/www.random.org\/","key":"6_CR20"},{"unstructured":"Side channel attacks database (2009), http:\/\/www.sidechannelattacks.com","key":"6_CR21"},{"doi-asserted-by":"crossref","unstructured":"Standaert, F.X., Malkin, T., Yung, M.: A unified framework for the analysis of side-channel key recovery attacks. In: Advances in Cryptography, Eurocrypt (2009)","key":"6_CR22","DOI":"10.1007\/978-3-642-01001-9_26"},{"doi-asserted-by":"crossref","unstructured":"Standaert, F.X., Peeters, E., Archambeau, C., Quisquater, J.J.: Towards security limits in side-channel attacks. In: Proc. CHES Workshop (2006)","key":"6_CR23","DOI":"10.1007\/11894063_3"},{"doi-asserted-by":"crossref","unstructured":"Tromer, E., Shamir, A., Osvik, D.: Efficient cache attacks on aes, and countermeasures. Journal of Cryptology (2009)","key":"6_CR24","DOI":"10.1007\/s00145-009-9049-y"},{"doi-asserted-by":"crossref","unstructured":"Tullsen, D., Eggers, S., Levy, H.: Simultaneous multithreading: Maximizing on-chip parallelism. In: International Symposium on Computer Architecture (1995)","key":"6_CR25","DOI":"10.1145\/223982.224449"},{"doi-asserted-by":"crossref","unstructured":"Wang, Z., Lee, R.: New cache designs for thwarting software cache-based side channel attacks. In: Proc. International Symposium on Computer Architecture (ISCA) (June 2007)","key":"6_CR26","DOI":"10.1145\/1250662.1250723"},{"unstructured":"Wang, Z., Lee, R.: A novel cache architecture with enhanced performance and security. In: Proc. International Symposium on Microarchitecture (MICRO) (December 2008)","key":"6_CR27"}],"container-title":["Lecture Notes in Computer Science","Computer Network Security"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-14706-7_6.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,24]],"date-time":"2025-02-24T03:00:57Z","timestamp":1740366057000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-14706-7_6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"ISBN":["9783642147050","9783642147067"],"references-count":27,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-14706-7_6","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2010]]}}}