{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T05:27:04Z","timestamp":1740547624015,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642157653"},{"type":"electronic","value":"9783642157660"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-3-642-15766-0_80","type":"book-chapter","created":{"date-parts":[[2010,9,2]],"date-time":"2010-09-02T20:41:05Z","timestamp":1283460065000},"page":"490-494","source":"Crossref","is-referenced-by-count":0,"title":["4T Carry Look Ahead Adder Design Using MIFG"],"prefix":"10.1007","author":[{"given":"P. H. ST.","family":"Murthy","sequence":"first","affiliation":[]},{"given":"L.","family":"Madan Mohan","sequence":"additional","affiliation":[]},{"given":"V.","family":"Sreenivasa Rao","sequence":"additional","affiliation":[]},{"given":"V.","family":"Malleswara Rao","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"80_CR1","unstructured":"Modeling multiple-input floating-gate transistors for analog signal pirqcessing. 1997 IEEE International Symposium on Circuits and Systems, Hong Kong (June 9-12, 1997)"},{"key":"80_CR2","volume-title":"Operation and Modeling of The MOS Transistor","author":"Y. Tsividis","year":"1999","unstructured":"Tsividis, Y.: Operation and Modeling of The MOS Transistor. Mc Graw-Hill, New York (1999)"},{"issue":"6","key":"80_CR3","doi-asserted-by":"publisher","first-page":"1444","DOI":"10.1109\/16.137325","volume":"39","author":"T. Shibata","year":"1992","unstructured":"Shibata, T., Ohmi, T.: A functional MOS transistor featuring gate-level weighted sum and threshold operations. IEEE Trans. on Electron Devices\u00a039(6), 1444\u20131455 (1992)","journal-title":"IEEE Trans. on Electron Devices"},{"key":"80_CR4","doi-asserted-by":"crossref","unstructured":"Srivastava, A., Venkata, H.N., Ajmera, P.K.: A novel scheme for a higher bandwidth sensor readout. In: Proc. of SPIE, vol.\u00a04700, pp. 17\u201328 (2002)","DOI":"10.1117\/12.475050"},{"key":"80_CR5","doi-asserted-by":"publisher","first-page":"1700","DOI":"10.1109\/16.536816","volume":"43","author":"W. Weber","year":"1996","unstructured":"Weber, W., Prange, S.J., Thewes, R., Wohlrab, E., Luck, A.: On the application of the neuron MOS transistor principle for modern VLSI design. IEEE Trans. on Electron Devices\u00a043, 1700\u20131708 (1996)","journal-title":"IEEE Trans. on Electron Devices"},{"key":"80_CR6","doi-asserted-by":"crossref","unstructured":"Yin, L., Embadi, S.H.K., Sanchez-Sinencio, E.: A floating gate MOSFET D\/A converter. In: Proc. of IEEE International Symposium on Circuits and Systems, vol.\u00a01, pp. 409\u2013412 (1997)","DOI":"10.1109\/ISCAS.1997.608754"},{"key":"80_CR7","doi-asserted-by":"publisher","first-page":"102","DOI":"10.1109\/82.913193","volume":"48","author":"E. Rodriguez-Villegas","year":"2001","unstructured":"Rodriguez-Villegas, E., Huertas, G., Avedillo, M.J., Quintana, J.M., Rueda, A.: A practical floating-gate Muller-C element using vMOS threshold gates. IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing\u00a048, 102\u2013106 (2001)","journal-title":"IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing"},{"key":"80_CR8","volume-title":"Digital Integrated Circuits- A Design Perspective","author":"J.M. Rabaey","year":"1996","unstructured":"Rabaey, J.M.: Digital Integrated Circuits- A Design Perspective. Prentice Hall, Englewood Cliffs (1996)"},{"key":"80_CR9","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1109\/82.996055","volume":"49","author":"H.T. Bui","year":"2002","unstructured":"Bui, H.T., Wang, Y., Jiang, Y.: Design and analysis of low-power 10- transistor full adders using novel XOR-XNOR gates. IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing\u00a049, 25\u201330 (2002)","journal-title":"IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing"},{"key":"80_CR10","doi-asserted-by":"publisher","first-page":"780","DOI":"10.1109\/4.303715","volume":"29","author":"J.M. Wang","year":"1994","unstructured":"Wang, J.M., Fang, S.C., Fang, W.C.: New efficient designs for XOR and XNOR functions on transistor level. IEEE J. of Solid State Circuits\u00a029, 780\u2013786 (1994)","journal-title":"IEEE J. of Solid State Circuits"},{"key":"80_CR11","doi-asserted-by":"publisher","first-page":"478","DOI":"10.1109\/82.842117","volume":"47","author":"A.M. Shams","year":"2000","unstructured":"Shams, A.M., Bayoumi, M.A.: A novel high-performance CMOS 1-bit full-adder cell. IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing\u00a047, 478\u2013481 (2000)","journal-title":"IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing"},{"key":"80_CR12","unstructured":"Rodriguez-villegas, E., Quintana, J.M., Avidillaand, M.J., Rueda, A.: High speed low power logic circuits using floating gates. In: IEEE international symposium on circuits and systems, Transaction on circuits and systems"},{"key":"80_CR13","unstructured":"http:\/\/www.wikipedia.org\/"},{"key":"80_CR14","unstructured":"http:\/\/etd.lsu.edu\/docs\/available\/etd-1011103-211310\/unrestricted\/Srinivasan_thesis.pdf"}],"container-title":["Communications in Computer and Information Science","Information and Communication Technologies"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-15766-0_80.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T13:42:53Z","timestamp":1740490973000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-15766-0_80"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"ISBN":["9783642157653","9783642157660"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-15766-0_80","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2010]]}}}