{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T04:42:59Z","timestamp":1769920979259,"version":"3.49.0"},"publisher-location":"Berlin, Heidelberg","reference-count":81,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783642173097","type":"print"},{"value":"9783642173103","type":"electronic"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-17310-3_5","type":"book-chapter","created":{"date-parts":[[2011,9,15]],"date-time":"2011-09-15T13:34:22Z","timestamp":1316093662000},"page":"125-179","source":"Crossref","is-referenced-by-count":13,"title":["Evolution of Electronic Circuits"],"prefix":"10.1007","author":[{"given":"Lukas","family":"Sekanina","sequence":"first","affiliation":[]},{"given":"James Alfred","family":"Walker","sequence":"additional","affiliation":[]},{"given":"Paul","family":"Kaufmann","sequence":"additional","affiliation":[]},{"given":"Marco","family":"Platzner","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"5_CR1","unstructured":"Genetic Programming. http:\/\/en.wikipedia.org\/wiki\/Genetic_programming"},{"key":"5_CR2","doi-asserted-by":"publisher","first-page":"248","DOI":"10.1109\/MICRO.1999.809463","volume-title":"Proc. ACM\/IEEE International Symposium on Microarchitecture","author":"D.H. Albonesi","year":"1999","unstructured":"Albonesi, D.H.: Selective Cache Ways: On-demand Cache Resource Allocation. In: Proc. ACM\/IEEE International Symposium on Microarchitecture, pp. 248\u2013259. IEEE Computer Society (1999)"},{"issue":"1","key":"5_CR3","doi-asserted-by":"publisher","first-page":"11","DOI":"10.1023\/B:GENP.0000017009.11392.e2","volume":"5","author":"B. Ali","year":"2004","unstructured":"Ali, B., Almaini, A.E.A., Kalganova, T.: Evolutionary Algorithms and Their Use in the Design of Sequential Logic Circuits. Genetic Programming and Evolvable Machines 5(1), 11\u201329 (2004)","journal-title":"Genetic Programming and Evolvable Machines"},{"issue":"3\u20134","key":"5_CR4","doi-asserted-by":"publisher","first-page":"199","DOI":"10.1023\/B:AIRE.0000006609.72718.dd","volume":"20","author":"T. Aoki","year":"2003","unstructured":"Aoki, T., Homma, N., Higuchi, T.: Evolutionary Synthesis of Arithmetic Circuit Structures. Artificial Intelligence Review 20(3\u20134), 199\u2013232 (2003)","journal-title":"Artificial Intelligence Review"},{"key":"5_CR5","doi-asserted-by":"publisher","first-page":"153","DOI":"10.1088\/0957-4484\/10\/2\/309","volume":"10","author":"A. Asenov","year":"1999","unstructured":"Asenov, A.: Random Dopant Induced Threshold Voltage Lowering and Fluctuations in sub 50 nm MOSFETs: A Statistical 3D \u2018Atomistic\u2019 Simulation Study. Nanotechnology 10, 153\u2013158 (1999)","journal-title":"Nanotechnology"},{"key":"5_CR6","volume-title":"International Conference of CMOS Variability","author":"A. Asenov","year":"2007","unstructured":"Asenov, A.: Variability in the Next Generation CMOS Technologies and Impact on Design. In: International Conference of CMOS Variability (2007)"},{"issue":"2","key":"5_CR7","doi-asserted-by":"publisher","first-page":"59","DOI":"10.1109\/2.982917","volume":"35","author":"T. Austin","year":"2002","unstructured":"Austin, T., Larson, E., Ernst, D.: SimpleScalar: An Infrastructure for Computer System Modeling. Computer 35(2), 59\u201367 (2002)","journal-title":"Computer"},{"key":"5_CR8","unstructured":"Biovision: EMG Amplifier. www.biovison.eu"},{"key":"5_CR9","volume-title":"Proc. European Conference on Technically Assisted Rehabilitation","author":"A. Boschmann","year":"2009","unstructured":"Boschmann, A., Kaufmann, P., Platzner, M., Winkler, M.: Towards Multi-movement Hand Prostheses: Combining Adaptive Classification with High Precision Sockets. In: Proc. European Conference on Technically Assisted Rehabilitation (2009)"},{"key":"5_CR10","first-page":"1580","volume-title":"Proc. of the Genetic and Evolutionary Computation Conference","author":"J. Clegg","year":"2007","unstructured":"Clegg, J., Walker, J.A., Miller, J.F.: A New Crossover Technique for Cartesian Genetic Programming. In: Proc. of the Genetic and Evolutionary Computation Conference, pp. 1580\u20131587 (2007)"},{"key":"5_CR11","unstructured":"Classic Test Still Images. http:\/\/hlevkin.com"},{"key":"5_CR12","doi-asserted-by":"publisher","first-page":"181","DOI":"10.1109\/4235.996017","volume":"6","author":"K. Deb","year":"2002","unstructured":"Deb, K., Pratap, A., Agarwal, S., Meyarivan, T.: A Fast and Elitist Multi-Objective Genetic Algorithm: NSGA-II. IEEE Transactions on Evolutionary Computation 6, 181\u2013197 (2002)","journal-title":"IEEE Transactions on Evolutionary Computation"},{"key":"5_CR13","doi-asserted-by":"publisher","first-page":"105","DOI":"10.1016\/S0167-9317(99)00348-2","volume":"48","author":"W. Eccleston","year":"1999","unstructured":"Eccleston, W.: The Effect of Polysilicon Grain Boundaries on MOS Based Devices. Microelectronic Engineering 48, 105\u2013108 (1999)","journal-title":"Microelectronic Engineering"},{"key":"5_CR14","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1007\/3-540-45355-5_4","volume-title":"Proc. European Conference on Genetic Programming","author":"M. Erba","year":"2001","unstructured":"Erba, M., Rossi, R., Liberali, V., Tettamanzi, A.: An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters. In: Proc. European Conference on Genetic Programming, vol. 2038, pp. 36\u201350. Springer (2001)"},{"key":"5_CR15","first-page":"245","volume-title":"Proc. Genetic and Evolutionary Computation Conference","author":"Z. Gajda","year":"2007","unstructured":"Gajda, Z., Sekanina, L.: Reducing the Number of Transistors in Digital Circuits Using Gate-Level Evolutionary Design. In: Proc. Genetic and Evolutionary Computation Conference, pp. 245\u2013252. ACM Press (2007)"},{"key":"5_CR16","doi-asserted-by":"publisher","first-page":"1599","DOI":"10.1109\/CEC.2009.4983133","volume-title":"Proc. IEEE Congress on Evolutionary Computation","author":"Z. Gajda","year":"2009","unstructured":"Gajda, Z., Sekanina, L.: Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming. In: Proc. IEEE Congress on Evolutionary Computation, pp. 1599\u20131604. IEEE (2009)"},{"key":"5_CR17","series-title":"LNCS","first-page":"13","volume-title":"Proc. International Conference on Evolvable Systems","author":"Z. Gajda","year":"2010","unstructured":"Gajda, Z., Sekanina, L.: An Efficient Selection Strategy for Digital Circuit Evolution. In: Proc. International Conference on Evolvable Systems, LNCS, vol. 6274, pp. 13\u201324. Springer (2010)"},{"key":"5_CR18","doi-asserted-by":"publisher","first-page":"32","DOI":"10.1109\/AHS.2008.12","volume-title":"Proc. NASA\/ESA Conference on Adaptive Hardware and Systems","author":"K. Glette","year":"2008","unstructured":"Glette, K., Gruber, T., Kaufmann, P., Torresen, J., Sick, B., Platzner, M.: Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. In: Proc. NASA\/ESA Conference on Adaptive Hardware and Systems, pp. 32\u201339. IEEE Computer Society (2008)"},{"key":"5_CR19","series-title":"LNCS","first-page":"66","volume-title":"Proc. International Conference on Evolvable Systems","author":"K. Glette","year":"2005","unstructured":"Glette, K., Torresen, J.: A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device. In: Proc. International Conference on Evolvable Systems, LNCS, vol. 3637, pp. 66\u201375. Springer Berlin \/ Heidelberg (2005)"},{"key":"5_CR20","series-title":"LNCS","first-page":"22","volume-title":"Proc. International Conference on Evolvable Systems","author":"K. Glette","year":"2008","unstructured":"Glette, K., Torresen, J., Kaufmann, P., Platzner, M.: A Comparison of Evolvable Hardware Architectures for Classification Tasks. In: Proc. International Conference on Evolvable Systems, LNCS, pp. 22\u201333. Springer (2008)"},{"key":"5_CR21","series-title":"LNCS","first-page":"271","volume-title":"Applications of Evolutionary Computing","author":"K. Glette","year":"2007","unstructured":"Glette, K., Torresen, J., Yasunaga, M.: An Online EHW Pattern Recognition System Applied to Face Image Recognition. In: Applications of Evolutionary Computing, LNCS, vol. 4448, pp. 271\u2013280. Springer (2007)"},{"key":"5_CR22","volume-title":"Anatomy of the Human Body","author":"H. Gray","year":"1918","unstructured":"Gray, H.: Anatomy of the Human Body (1918). Retrieved from Wikimedia Commons"},{"key":"5_CR23","volume-title":"Introduction to Evolvable Hardware","author":"G. Greenwood","year":"2007","unstructured":"Greenwood, G., Tyrrell, A.M.: Introduction to Evolvable Hardware. IEEE Press (2007)"},{"key":"5_CR24","first-page":"4842","volume-title":"Engineering in Medicine and Biology Society","author":"L. Hargrove","year":"2007","unstructured":"Hargrove, L., Losier, Y., Lock, B., Englehart, K., Hudgins, B.: A Real-Time Pattern Recognition Based Myoelectric Control Usability Study Implemented in a Virtual Environment. In: Engineering in Medicine and Biology Society, pp. 4842\u20134845. IEEE Press (2007)"},{"key":"5_CR25","series-title":"LNCS","doi-asserted-by":"crossref","first-page":"118","DOI":"10.1007\/3-540-61093-6_6","volume-title":"Towards Evolvable Hardware: The evolutionary Engineering Approach","author":"T. Higuchi","year":"1996","unstructured":"Higuchi, T., Iwata, M., Kajitani, I., Iba, H., Hirao, Y., Manderick, B., Furuya, T.: Evolvable Hardware and its Applications to Pattern Recognition and Fault-Tolerant Systems. In: Towards Evolvable Hardware: The evolutionary Engineering Approach, LNCS, vol. 1062, pp. 118\u2013135. Springer (1996)"},{"key":"5_CR26","doi-asserted-by":"publisher","DOI":"10.1007\/0-387-31238-2","volume-title":"Evolvable Hardware","author":"T. Higuchi","year":"2006","unstructured":"Higuchi, T., Liu, Y., Yao, X.: Evolvable Hardware. Springer (2006)"},{"key":"5_CR27","volume-title":"Proc. International Conference on Ph.D. Research in Microelectronics & Electronics (PRIME)","author":"J.A. Hilder","year":"2009","unstructured":"Hilder, J.A., Walker, J.A., Tyrrell, A.M.: Designing Variability Tolerant Logic using Evolutionary Algorithms. In: Proc. International Conference on Ph.D. Research in Microelectronics & Electronics (PRIME) (2009)"},{"key":"5_CR28","series-title":"Proc. IEEE Symposium Series on Computational Intelligence","doi-asserted-by":"publisher","first-page":"17","DOI":"10.1109\/WEAH.2009.4925663","volume-title":"Proc. IEEE Workshop on Evolvable and Adaptive Hardware","author":"J.A. Hilder","year":"2009","unstructured":"Hilder, J.A., Walker, J.A., Tyrrell, A.M.: Optimisation of Variability Tolerant Logic Cells using Multiple Voltage Supplies. In: Proc. IEEE Workshop on Evolvable and Adaptive Hardware, Proc. IEEE Symposium Series on Computational Intelligence, pp. 17\u201324. IEEE (2009)"},{"key":"5_CR29","doi-asserted-by":"publisher","first-page":"2273","DOI":"10.1109\/CEC.2009.4983223","volume-title":"Proc. IEEE Congress on Evolutionary Computation","author":"J.A. Hilder","year":"2009","unstructured":"Hilder, J.A., Walker, J.A., Tyrrell, A.M.: Optimising Variability Tolerant Standard Cell Libraries. In: Proc. IEEE Congress on Evolutionary Computation, pp. 2273\u20132280. IEEE (2009)"},{"issue":"5","key":"5_CR30","doi-asserted-by":"crossref","first-page":"307","DOI":"10.1007\/s00500-003-0287-x","volume":"8","author":"B.I. Hounsell","year":"2004","unstructured":"Hounsell, B.I., Arslan, T., Thomson, R.: Evolutionary Design and Adaptation of High Performance Digital Filters within an Embedded Reconfigurable Fault Tolerant Hardware Platform. Soft Computing 8(5), 307\u2013317 (2004)","journal-title":"Soft Computing"},{"key":"5_CR31","first-page":"84","volume-title":"Proc. International Symposium on Measurement, Analysis and Modeling of Human Functions","author":"I. Kajitani","year":"2001","unstructured":"Kajitani, I., Sekita, I., Otsu, N., Higuchi, T.: Improvements to the Action Decision Rate for a Multi-Function Prosthetic Hand. In: Proc. International Symposium on Measurement, Analysis and Modeling of Human Functions, pp. 84\u201389 (2001)"},{"key":"5_CR32","doi-asserted-by":"publisher","first-page":"54","DOI":"10.1109\/EH.1999.785435","volume-title":"Proc. NASA\/DoD Workshop on Evolvable Hardware","author":"T. Kalganova","year":"1999","unstructured":"Kalganova, T., Miller, J.F.: Evolving More Efficient Digital Circuits by Allowing Circuit Layout Evolution and Multi-Objective Fitness. In: Proc. NASA\/DoD Workshop on Evolvable Hardware, pp. 54\u201363. IEEE Computer Society (1999)"},{"key":"5_CR33","doi-asserted-by":"crossref","first-page":"447","DOI":"10.1109\/AHS.2007.73","volume-title":"Proc. NASA\/ESA Conference on Adaptive Hardware and Systems","author":"P. Kaufmann","year":"2007","unstructured":"Kaufmann, P., Platzner, M.: MOVES: A Modular Framework for Hardware Evolution. In: Proc. NASA\/ESA Conference on Adaptive Hardware and Systems, pp. 447\u2013454. IEEE (2007)"},{"key":"5_CR34","first-page":"1219","volume-title":"Proc. Genetic and Evolutionary Computation Conference\u00a0(GECCO\u201908)","author":"P. Kaufmann","year":"2008","unstructured":"Kaufmann, P., Platzner, M.: Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In: Proc. Genetic and Evolutionary Computation Conference\u00a0(GECCO\u201908), pp. 1219\u20131226. ACM Press (2008)"},{"key":"5_CR35","doi-asserted-by":"publisher","first-page":"11","DOI":"10.1109\/AHS.2009.26","volume-title":"Proc. NASA\/ESA Conference on Adaptive Hardware and Systems","author":"P. Kaufmann","year":"2009","unstructured":"Kaufmann, P., Plessl, C., Platzner, M.: EvoCaches: Application-specific Adaptation of Cache Mappings. In: Proc. NASA\/ESA Conference on Adaptive Hardware and Systems, pp. 11\u201318. IEEE Computer Society (2009)"},{"key":"5_CR36","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-662-06728-4","volume-title":"Digital Signal Processing with Field Programmable Gate Arrays","author":"U. Meyer-Baese","year":"2004","unstructured":"Meyer-Baese, U.: Digital Signal Processing with Field Programmable Gate Arrays. Springer (2004)"},{"key":"5_CR37","first-page":"1127","volume-title":"Proc. Genetic and Evolutionary Computation Conference","author":"J.F. Miller","year":"1999","unstructured":"Miller, J.F.: Digital Filter Design at Gate-level Using Evolutionary Algorithms. In: Proc. Genetic and Evolutionary Computation Conference, pp. 1127\u20131134. Morgan Kaufmann (1999)"},{"key":"5_CR38","series-title":"LNCS","first-page":"17","volume-title":"Proc. Workshop on Evolutionary Image Analysis and Signal Processing","author":"J.F. Miller","year":"1999","unstructured":"Miller, J.F.: Evolution of Digital Filters Using a Gate Array Model. In: Proc. Workshop on Evolutionary Image Analysis and Signal Processing, LNCS, vol. 1596, pp. 17\u201330. Springer (1999)"},{"issue":"1","key":"5_CR39","doi-asserted-by":"publisher","first-page":"8","DOI":"10.1023\/A:1010016313373","volume":"1","author":"J.F. Miller","year":"2000","unstructured":"Miller, J.F., Job, D., Vassilev, V.K.: Principles in the Evolutionary Design of Digital Circuits \u2013 Part I. Genetic Programming and Evolvable Machines 1(1), 8\u201335 (2000)","journal-title":"Genetic Programming and Evolvable Machines"},{"key":"5_CR40","unstructured":"Moore, G.E.: Cramming More Components onto Integrated Circuits. Electronics 38 (1965)"},{"key":"5_CR41","volume-title":"International Conference on CMOS Variability","author":"V. Moroz","year":"2007","unstructured":"Moroz, V.: Design for Manufacturability: OPC and Stress Variations. In: International Conference on CMOS Variability (2007)"},{"key":"5_CR42","unstructured":"National Instruments: USB-6009. www.ni.com"},{"key":"5_CR43","unstructured":"Petley, G.: VLSI and ASIC Technology Standard Cell Library Design. www.vlsitechnology.org"},{"issue":"1\u20132","key":"5_CR44","doi-asserted-by":"publisher","first-page":"37","DOI":"10.1023\/A:1010068314282","volume":"1","author":"R. Poli","year":"2000","unstructured":"Poli, R., Page, J.: Solving High-Order Boolean Parity Problems with Smooth Uniform Crossover, Sub-Machine Code GP and Demes. Genetic Programming and Evolvable Machines 1(1\u20132), 37\u201356 (2000)","journal-title":"Genetic Programming and Evolvable Machines"},{"issue":"2","key":"5_CR45","doi-asserted-by":"crossref","first-page":"214","DOI":"10.1145\/342001.339685","volume":"28","author":"P. Ranganathan","year":"2000","unstructured":"Ranganathan, P., Adve, S., Jouppi, N.P.: Reconfigurable Caches and Their Application to Media Processing. Proc. International Symposium on Computer Architecture 28(2), 214\u2013224 (2000)","journal-title":"Proc. International Symposium on Computer Architecture"},{"key":"5_CR46","doi-asserted-by":"publisher","first-page":"31","DOI":"10.1109\/IOLTS.2008.23","volume-title":"Proc. IEEE International On-Line Testing Symposium","author":"R. Ruzicka","year":"2008","unstructured":"Ruzicka, R., Sekanina, L., Prokop, R.: Physical Demonstration of Polymorphic Self-checking Circuits. In: Proc. IEEE International On-Line Testing Symposium, pp. 31\u201336. IEEE (2008)"},{"key":"5_CR47","series-title":"Natural Computing","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-642-18609-7","volume-title":"Evolvable Components: From Theory to Hardware Implementations","author":"L. Sekanina","year":"2004","unstructured":"Sekanina, L.: Evolvable Components: From Theory to Hardware Implementations. Natural Computing. Springer (2004)"},{"key":"5_CR48","series-title":"LNCS","doi-asserted-by":"publisher","first-page":"185","DOI":"10.1007\/978-3-540-32003-6_19","volume-title":"Applications of Evolutionary Computing","author":"L. Sekanina","year":"2005","unstructured":"Sekanina, L.: Evolutionary Design of Gate-Level Polymorphic Digital Circuits. In: Applications of Evolutionary Computing, LNCS, vol. 3449, pp. 185\u2013194. Springer (2005)"},{"key":"5_CR49","doi-asserted-by":"publisher","first-page":"43","DOI":"10.1109\/AHS.2009.27","volume-title":"Proc. NASA\/ESA Conference on Adaptive Hardware and Systems","author":"L. Sekanina","year":"2009","unstructured":"Sekanina, L., Ruzicka, R., Gajda, Z.: Polymorphic FIR Filters with Backup Mode Enabling Power Savings. In: Proc. NASA\/ESA Conference on Adaptive Hardware and Systems, pp. 43\u201350. IEEE (2009)"},{"key":"5_CR50","doi-asserted-by":"publisher","first-page":"39","DOI":"10.1109\/WEAH.2009.4925666","volume-title":"Proc. of IEEE Symposium Series on Computational Intelligence - Workshop on Evolvable and Adaptive Hardware","author":"L. Sekanina","year":"2009","unstructured":"Sekanina, L., Ruzicka, R., Vasicek, Z., Prokop, R., Fujcik, L.: REPOMO32 \u2013 New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware. In: Proc. of IEEE Symposium Series on Computational Intelligence - Workshop on Evolvable and Adaptive Hardware, pp. 39\u201346. IEEE Computational Intelligence Society (2009)"},{"issue":"2","key":"5_CR51","first-page":"125","volume":"4","author":"L. Sekanina","year":"2008","unstructured":"Sekanina, L., Starecek, L., Kotasek, Z., Gajda, Z.: Polymorphic Gates in Design and Test of Digital Circuits. International Journal of Unconventional Computing 4(2), 125\u2013142 (2008)","journal-title":"International Journal of Unconventional Computing"},{"key":"5_CR52","doi-asserted-by":"publisher","first-page":"344","DOI":"10.1007\/11732242_31","volume-title":"Applications of Evolutionary Computing","author":"L. Sekanina","year":"2006","unstructured":"Sekanina, L., Vasicek, Z.: On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. In: Applications of Evolutionary Computing, 3907, pp. 344\u2013355. Springer (2006)"},{"key":"5_CR53","unstructured":"Seward, J.: bzip2: A Freely Available, Patent Free, High-quality Data Compressor (2009). www.bzip.org\/"},{"issue":"2","key":"5_CR54","doi-asserted-by":"publisher","first-page":"618","DOI":"10.1016\/j.asoc.2008.08.004","volume":"9","author":"A.P. Shanthi","year":"2009","unstructured":"Shanthi, A.P., Parthasarathi, R.: Practical and Scalable Evolution of Digital Circuits. Applied Soft Computing 9(2), 618\u2013624 (2009)","journal-title":"Applied Soft Computing"},{"key":"5_CR55","unstructured":"Shivakumar, P., Jouppi, N.P.: CACTI 3.0: An Integrated Cache Timing, Power, and Area Model. Tech. rep., COMPAQ Western Research Lab, Palo Alto, California 94301 USA (1999)"},{"key":"5_CR56","series-title":"LNCS","first-page":"34","volume-title":"Proc. International Conference on Evolvable Systems","author":"S.L. Smith","year":"2008","unstructured":"Smith, S.L., Greensted, A.J., Timmis, J.: Hardware Acceleration of an Immune Network Inspired Evolutionary Algorithm for Medical Diagnosis. In: Proc. International Conference on Evolvable Systems, LNCS, vol. 5216, pp. 34\u201346. Springer Berlin \/ Heidelberg (2008)"},{"key":"5_CR57","unstructured":"Sonowin: USI-01 USB Isolator. www.sonowin.de"},{"key":"5_CR58","doi-asserted-by":"publisher","first-page":"1237","DOI":"10.1109\/TCAD.2002.804109","volume":"21","author":"T. Sripramong","year":"2002","unstructured":"Sripramong, T., Toumazou, C.: The Invention of CMOS Amplifiers Using Genetic Programming and Current-Flow Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 21, 1237\u20131252 (2002)","journal-title":"IEEE Trans. on CAD of Integrated Circuits and Systems"},{"key":"5_CR59","first-page":"965","volume-title":"Proc. Int. Conf. on Parallel Processing","author":"M. Stanca","year":"2000","unstructured":"Stanca, M., Vassiliadis, S., Cotofana, S., Corporaal, H.: Hashed Addressed Caches for Embedded Pointer Based Codes. In: Proc. Int. Conf. on Parallel Processing, pp. 965\u2013968. Springer (2000)"},{"key":"5_CR60","first-page":"255","volume-title":"Proc. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop","author":"L. Starecek","year":"2008","unstructured":"Starecek, L., Sekanina, L., Kotasek, Z.: Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. In: Proc. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, pp. 255\u2013258. IEEE Computer Society (2008)"},{"key":"5_CR61","series-title":"LNCS","first-page":"291","volume-title":"Proc. International Conference on Evolvable Systems","author":"A. Stoica","year":"2001","unstructured":"Stoica, A., Zebulum, R.S., Keymeulen, D.: Polymorphic Electronics. In: Proc. International Conference on Evolvable Systems, LNCS, vol. 2210, pp. 291\u2013302. Springer (2001)"},{"issue":"5","key":"5_CR62","doi-asserted-by":"publisher","first-page":"1024","DOI":"10.1109\/TSMCB.2006.872259","volume":"36","author":"E. Stomeo","year":"2006","unstructured":"Stomeo, E., Kalganova, T., Lambert, C.: Generalized Disjunction Decomposition for Evolvable Hardware. IEEE Transaction Systems, Man and Cybernetics, Part B 36(5), 1024\u20131043 (2006)","journal-title":"IEEE Transaction Systems, Man and Cybernetics, Part B"},{"key":"5_CR63","volume-title":"Logical Effort \u2013 Designing Fast CMOS Circuits","author":"I. Sutherland","year":"1999","unstructured":"Sutherland, I., Sproull, B., Harris, D.: Logical Effort \u2013 Designing Fast CMOS Circuits. Morgan Kaufmann (1999)"},{"key":"5_CR64","first-page":"429","volume-title":"Smart Engineering System Design: Neural Networks, Fuzzy Logic, Evolutionary Programming, Data Mining, and Complex Systems (ANNIE)","author":"J. Torresen","year":"1999","unstructured":"Torresen, J.: Increased Complexity Evolution Applied to Evolvable Hardware. In: Smart Engineering System Design: Neural Networks, Fuzzy Logic, Evolutionary Programming, Data Mining, and Complex Systems (ANNIE), pp. 429\u2013436. ASME Press (1999)"},{"key":"5_CR65","doi-asserted-by":"publisher","first-page":"245","DOI":"10.1109\/EH.2000.869362","volume-title":"Proc. NASA\/DoD workshop on Evolvable Hardware","author":"J. Torresen","year":"2000","unstructured":"Torresen, J.: Scalable Evolvable Hardware Applied to Road Image Recognition. In: Proc. NASA\/DoD workshop on Evolvable Hardware, pp. 245\u2013252. IEEE Computer Society (2000)"},{"key":"5_CR66","unstructured":"The USC-SIPI Image Database. sipi.usc.edu\/database"},{"key":"5_CR67","first-page":"261","volume-title":"Proc. Int. Conf. on Architecture of Computing Systems (ARCS)","author":"H. Vandierendonck","year":"2008","unstructured":"Vandierendonck, H., Bosschere, K.D.: Constructing Optimal XOR-Functions to Minimize Cache Conflict Misses. In: Proc. Int. Conf. on Architecture of Computing Systems (ARCS), pp. 261\u2013272. Springer (2008)"},{"issue":"3","key":"5_CR68","doi-asserted-by":"publisher","first-page":"305","DOI":"10.1007\/s10710-011-9132-7","volume":"12","author":"Z. Vasicek","year":"2011","unstructured":"Vasicek, Z., Sekanina, L.: Formal Verification of Candidate Solutions for Post-Synthesis EvoluTionary Optimization in Evolvable Hardware. Genetic Programming and Evolvable Machines 12(3), 305\u2013327 (2011)","journal-title":"Genetic Programming and Evolvable Machines"},{"key":"5_CR69","series-title":"LNCS","first-page":"141","volume-title":"Proc. International Conference on Evolvable Systems","author":"Z. Vasicek","year":"2008","unstructured":"Vasicek, Z., Zadnik, M., Sekanina, L., Tobola, J.: On Evolutionary Synthesis of Linear Transforms in FPGA. In: Proc. International Conference on Evolvable Systems, LNCS, vol. 5216, pp. 141\u2013152. Springer (2008)"},{"key":"5_CR70","doi-asserted-by":"publisher","first-page":"151","DOI":"10.1109\/EH.2000.869353","volume-title":"Proc. NASA\/DoD Workshop on Evolvable Hardware","author":"V. Vassilev","year":"2000","unstructured":"Vassilev, V., Job, D., Miller, J.F.: Towards the Automatic Design of More Efficient Digital Circuits. In: J. Lohn, A. Stoica, D. Keymeulen, S. Colombano (eds.) Proc. NASA\/DoD Workshop on Evolvable Hardware, pp. 151\u2013160. IEEE Computer Society (2000)"},{"key":"5_CR71","first-page":"539","volume-title":"Proc. Genetic and Evolutionary Computation Conference","author":"V.K. Vassilev","year":"2000","unstructured":"Vassilev, V.K., Miller, J.F.: Embedding Landscape Neutrality to Build a Bridge from the Conventional to a More Efficient Three-Bit Multiplier Circuit. In: Proc. Genetic and Evolutionary Computation Conference, p. 539 (2000)"},{"key":"5_CR72","doi-asserted-by":"crossref","unstructured":"Voronenko, Y., Puschel, M.: Multiplierless Multiple Constant Multiplication. ACM Transactions on Algorithms 3(2) (2007)","DOI":"10.1145\/1240233.1240234"},{"key":"5_CR73","volume-title":"Digital Design: Principles and Practices","author":"J.F. Wakerly","year":"2000","unstructured":"Wakerly, J.F.: Digital Design: Principles and Practices, 3rd edn. Prentice Hall, New Jersey, US (2000)","edition":"3"},{"key":"5_CR74","first-page":"308","volume-title":"Proc. International Conference on Evolvable Systems","author":"J.A. Walker","year":"2008","unstructured":"Walker, J.A., Hilder, J.A., Tyrrell, A.M.: Evolving Variability-Tolerant CMOS Designs. In: Proc. International Conference on Evolvable Systems, pp. 308\u2013319. Springer (2008)"},{"key":"5_CR75","doi-asserted-by":"publisher","first-page":"1591","DOI":"10.1109\/CEC.2009.4983132","volume-title":"Proc. IEEE Congress on Evolutionary Computation","author":"J.A. Walker","year":"2009","unstructured":"Walker, J.A., Hilder, J.A., Tyrrell, A.M.: Towards Evolving Industry-Feasible Intrinsic Variability Tolerant CMOS Designs. In: Proc. IEEE Congress on Evolutionary Computation, pp. 1591\u20131598. IEEE (2009)"},{"issue":"4","key":"5_CR76","doi-asserted-by":"publisher","first-page":"30","DOI":"10.1145\/103085.103089","volume":"34","author":"G.K. Wallace","year":"1991","unstructured":"Wallace, G.K.: The JPEG Still Picture Compression Standard. Communications of the ACM 34(4), 30\u201344 (1991)","journal-title":"Communications of the ACM"},{"key":"5_CR77","doi-asserted-by":"publisher","first-page":"141","DOI":"10.1587\/elex.6.141","volume":"6","author":"J. Wang","year":"2009","unstructured":"Wang, J., Lee, C.H.: Evolutionary Design of Combinational Logic Circuits Using VRA Processor. IEICE Electronics Express 6, 141\u2013147 (2009)","journal-title":"IEICE Electronics Express"},{"key":"5_CR78","unstructured":"ARM10E Processor Family. http:\/\/www.arm.com\/products\/CPUs\/families\/ARM10EFamily.html"},{"key":"5_CR79","unstructured":"Zebulum, R., Pacheco, M., Vellasco, M.: Evolutionary Electronics \u2013 Automatic Design of Electronic Circuits and Systems by Genetic Algorithms. The CRC Press International Series on Computational Intelligence (2002)"},{"issue":"3","key":"5_CR80","first-page":"8","volume":"30","author":"R.S. Zebulum","year":"2006","unstructured":"Zebulum, R.S., Stoica, A.: Four-Function Logic Gate Controlled by Analog Voltage. NASA Tech Briefs 30(3), 8 (2006)","journal-title":"NASA Tech Briefs"},{"issue":"2","key":"5_CR81","doi-asserted-by":"publisher","first-page":"407","DOI":"10.1145\/993396.993405","volume":"3","author":"C. Zhang","year":"2004","unstructured":"Zhang, C., Vahid, F., Lysecky, R.: A Self-tuning Cache Architecture for Embedded Systems. Trans. on Embedded Computing Systems 3(2), 407\u2013425 (2004)","journal-title":"Trans. on Embedded Computing Systems"}],"container-title":["Natural Computing Series","Cartesian Genetic Programming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-17310-3_5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T20:08:59Z","timestamp":1675282139000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-642-17310-3_5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642173097","9783642173103"],"references-count":81,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-17310-3_5","relation":{},"ISSN":["1619-7127"],"issn-type":[{"value":"1619-7127","type":"print"}],"subject":[],"published":{"date-parts":[[2011]]}}}