{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,2]],"date-time":"2025-03-02T05:51:33Z","timestamp":1740894693174,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642177514"},{"type":"electronic","value":"9783642177521"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-17752-1_22","type":"book-chapter","created":{"date-parts":[[2011,1,13]],"date-time":"2011-01-13T02:52:42Z","timestamp":1294887162000},"page":"218-227","source":"Crossref","is-referenced-by-count":0,"title":["An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis"],"prefix":"10.1007","author":[{"given":"Oliver","family":"Schrape","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Frank","family":"Winkler","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steffen","family":"Zeidler","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Markus","family":"Petri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eckhard","family":"Grass","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ulrich","family":"Jagdhold","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"22_CR1","volume-title":"Design and Applications, Design, Simulation, and Applications","author":"R. Best","year":"2000","unstructured":"Best, R.: Design and Applications, Design, Simulation, and Applications. McGraw-Hill, New York (February 2000)"},{"issue":"2","key":"22_CR2","first-page":"679","volume":"38","author":"C.C. Chung","year":"2003","unstructured":"Chung, C.C., Lee, C.Y.: An all-digital phase-locked loop for high-speed clock generation. IEEE Journal of Solid-State Circuits\u00a038(2), 679\u2013682 (2003)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"22_CR3","doi-asserted-by":"crossref","unstructured":"Herzel, F., Osmany, S.A., Hu, K., Schmalz, K., Jagdhold, U., Scheytt, J.C., Schrape, O., Winkler, W., Follmann, R., Kohl, D.K.T., Kersten, O., Podrebersek, T., Heyer, H.V., Winkler, F.: An integrated 8-12 ghz fractional-n frequency synthesizer in sige bicmos for satellite communications. In: Analog Integrated Circuits and Signal Processing (January 2010)","DOI":"10.1007\/s10470-010-9454-z"},{"key":"22_CR4","doi-asserted-by":"publisher","first-page":"89","DOI":"10.1023\/A:1016032010310","volume":"32","author":"S. Li","year":"2002","unstructured":"Li, S., Ismail, M.: A 7 ghz 1.5-v dual-modulus prescaler in 0.18 \u03bcm copper-cmos technology. Analog Integrated Circuits and Signal Processing\u00a032, 89\u201395 (2002)","journal-title":"Analog Integrated Circuits and Signal Processing"},{"key":"22_CR5","unstructured":"Moorthi, S., Meganathan, D., Janarthanan, D., Kumar, P.P., Perinbam, J.R.P.: Low jitter adpll based clock generator for high speed soc applications. In: Proceedings of World Academy of Science, Engineering and Technology, vol.\u00a032 (August 2008)"},{"issue":"5","key":"22_CR6","doi-asserted-by":"publisher","first-page":"700","DOI":"10.1109\/4.509852","volume":"31","author":"P. Nilsson","year":"1996","unstructured":"Nilsson, P., Torkelson, M.: A monolitic digital clock-generator for on-chip clocking of custom dsp\u2019s. IEEE Journal of Solid-State Circuits\u00a031(5), 700\u2013706 (1996)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"22_CR7","doi-asserted-by":"crossref","unstructured":"Olsson, T., Nilsson, P., Meincke, T., Hemam, A., Torkelson, M.: A digitally controlled low-power clock multiplier for globally asynchronous locally synchronous designs. In: IEEE International Symposium on Circuits and Systems, vol.\u00a03, pp. 13\u201316 (2000)","DOI":"10.1109\/ISCAS.2000.855983"},{"key":"22_CR8","unstructured":"Olsson, T., Nilsson, P.: A Digital PLL made from Standard Cells. In: European Conference on Circuit Theory and Design, ECCTD 2001 (August 2001)"},{"key":"22_CR9","unstructured":"Reddy, B.S.P., Krishnaparsad, N., Moorthi, S., Perinbam, J.R.P.: An All Digital Phase Locked Loop for Ultra Fast Locking. In: Proceedings of National Conference on Engineering Trends in Engineering and Technology (2008)"},{"key":"22_CR10","doi-asserted-by":"crossref","unstructured":"Sheng, D., Chung, C.C., Lee, C.Y.: A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications. In: IEEE Asia Pacific Conference on Circuits and Systems (2006)","DOI":"10.1109\/APCCAS.2006.342325"},{"key":"22_CR11","doi-asserted-by":"crossref","unstructured":"Zhuang, J., Du, Q., Kwasniewski, T.: Event-driven modeling and simulation of an digital pll. In: Proceedings of the IEEE International Behavioral Modeling and Simulation Workshop (2006)","DOI":"10.1109\/BMAS.2006.283472"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-17752-1_22","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T17:27:26Z","timestamp":1740850046000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-17752-1_22"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642177514","9783642177521"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-17752-1_22","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}