{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,16]],"date-time":"2026-06-16T14:49:24Z","timestamp":1781621364603,"version":"3.54.5"},"publisher-location":"Berlin, Heidelberg","reference-count":21,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783642179549","type":"print"},{"value":"9783642179556","type":"electronic"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-17955-6_14","type":"book-chapter","created":{"date-parts":[[2011,1,17]],"date-time":"2011-01-17T01:29:00Z","timestamp":1295227740000},"page":"191-205","source":"Crossref","is-referenced-by-count":4,"title":["Correlation Power Analysis Based on Switching Glitch Model"],"prefix":"10.1007","author":[{"given":"Hongying","family":"Liu","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Guoyu","family":"Qian","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Satoshi","family":"Goto","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yukiyasu","family":"Tsunoo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","reference":[{"key":"14_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"388","DOI":"10.1007\/3-540-48405-1_25","volume-title":"Advances in Cryptology - CRYPTO \u201999","author":"P. Kocher","year":"1999","unstructured":"Kocher, P., Jaffe, J., Jun, B.: Differential Power Analysis. In: CRYPTO 1999. LNCS, vol.\u00a01666, pp. 388\u2013397. Springer, Heidelberg (1999)"},{"key":"14_CR2","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1007\/978-3-540-28632-5_2","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2004","author":"E. Brier","year":"2004","unstructured":"Brier, E., Clavier, C., Olivier, F.: Correlation Power Analysis with a Leakage Model. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol.\u00a03156, pp. 16\u201329. Springer, Heidelberg (2004)"},{"key":"14_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"174","DOI":"10.1007\/11894063_14","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2006","author":"T. Le","year":"2006","unstructured":"Le, T., Cl\u00e9di\u00e8re, J., Canovas, C., et al.: A proposition for correlation power analysis enhancement. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol.\u00a04249, p. 174. Springer, Heidelberg (2006)"},{"key":"14_CR4","doi-asserted-by":"crossref","unstructured":"Katashita, T., Satoh, A., Sugawara, T., et al.: Enhanced Correlation Power Analysis Using Key Screening Technique. In: Proceedings of Reconfigurable Computing and FPGAs (ReConFig 2008), December 3-5, pp. 403\u2013408 (2008)","DOI":"10.1109\/ReConFig.2008.16"},{"issue":"1","key":"14_CR5","doi-asserted-by":"publisher","first-page":"52","DOI":"10.1016\/j.vlsi.2005.12.013","volume":"40","author":"E. Peeters","year":"2007","unstructured":"Peeters, E., Standaert, F.X., Quisquater, J.J.: Power and electromagnetic analysis: Improved model, consequences and comparisons. Integration, the VLSI Journal\u00a040(1), 52\u201360 (2007)","journal-title":"Integration, the VLSI Journal"},{"key":"14_CR6","unstructured":"National Institute of Standards and Technology (NIST) of U.S. Department of Commerce: FIPS 197: Advanced Encryption Standard (2001)"},{"key":"14_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"343","DOI":"10.1007\/3-540-36552-4_24","volume-title":"Information Security and Cryptology - ICISC 2002","author":"S. Mangard","year":"2003","unstructured":"Mangard, S.: A simple power analysis attack on implementation of the AES expansion. In: Lee, P.J., Lim, C.H. (eds.) ICISC 2002. LNCS, vol.\u00a02587, pp. 343\u2013358. Springer, Heidelberg (2003)"},{"key":"14_CR8","doi-asserted-by":"crossref","unstructured":"Ors, S.B., Gurkaynak, F., Oswald, E., et al.: Power-Analysis Attack on an ASIC AES implementation. In: Proceedings of ITCC 2004, Las Vegas, April 5-7 (2004)","DOI":"10.1109\/ITCC.2004.1286711"},{"issue":"3","key":"14_CR9","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1166\/jolpe.2006.100","volume":"2","author":"Y. Lu","year":"2006","unstructured":"Lu, Y., Agrawal, V.D.: CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. Journal of Low Power Electronics\u00a02(3), 1\u201310 (2006)","journal-title":"Journal of Low Power Electronics"},{"issue":"4","key":"14_CR10","doi-asserted-by":"publisher","first-page":"538","DOI":"10.1109\/TVLSI.2003.812295","volume":"11","author":"A. Raghunathan","year":"2003","unstructured":"Raghunathan, A., Dey, S., Jha, N.K.: High-level macro-modeling and estimation techniques for switching activity and power consumption. IEEE Transactions on Very Large Scale Integration (VLSI) Systems\u00a011(4), 538\u2013557 (2003)","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"14_CR11","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"351","DOI":"10.1007\/978-3-540-30574-3_24","volume-title":"Topics in Cryptology \u2013 CT-RSA 2005","author":"S. Mangard","year":"2005","unstructured":"Mangard, S., Popp, T., Gammel, B.M.: Side-channel Leakage of Masked CMOS Gates. In: Menezes, A. (ed.) CT-RSA 2005. LNCS, vol.\u00a03376, pp. 351\u2013365. Springer, Heidelberg (2005)"},{"key":"14_CR12","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"76","DOI":"10.1007\/11894063_7","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2006","author":"S. Mangard","year":"2006","unstructured":"Mangard, S., Schramm, K.: Pinpointing the side-channel leakage of masked AES hardware implementations. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol.\u00a04249, pp. 76\u201390. Springer, Heidelberg (2006)"},{"issue":"1","key":"14_CR13","doi-asserted-by":"publisher","first-page":"169","DOI":"10.1093\/ietfec\/e90-a.1.169","volume":"E90-A","author":"M. Saeki","year":"2007","unstructured":"Saeki, M., Suzuki, D., Ichikawa, T.: Leakage analysis of DPA Countermeasures at the Logic Level. IEICE transactions on fundamentals of electronics, communications and computer sciences\u00a0E90-A(1), 169\u2013178 (2007)","journal-title":"IEICE transactions on fundamentals of electronics, communications and computer sciences"},{"issue":"1","key":"14_CR14","doi-asserted-by":"publisher","first-page":"160","DOI":"10.1093\/ietfec\/e90-a.1.160","volume":"E90-A","author":"D. Suzuki","year":"2007","unstructured":"Suzuki, D., Saeki, M., Ichikawa, T.: Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level. IEICE transactions on fundamentals of electronics, communications and computer sciences\u00a0E90-A(1), 160\u2013168 (2007)","journal-title":"IEICE transactions on fundamentals of electronics, communications and computer sciences"},{"key":"14_CR15","doi-asserted-by":"crossref","unstructured":"Najm, F.N.: Power estimation techniques for integrated circuits. In: Proceedings of the International Conference on Computer-Aided Design, California, United States, pp. 492\u2013499 (1995)","DOI":"10.1109\/ICCAD.1995.480162"},{"key":"14_CR16","unstructured":"Liu, X., Papaefthymiou, M.C.: A statistical model of input glitch propagation and its application in power macromodeling. Journal of Power\u00a010, 10"},{"key":"14_CR17","unstructured":"Liu, X., Papaefthymiou, M.C.: Incorporation of input glitches into power macromodeling. In: Proceedings of IEEE International Symposium on Circuits and Systems (2002)"},{"key":"14_CR18","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"398","DOI":"10.1007\/3-540-48405-1_26","volume-title":"Advances in Cryptology - CRYPTO \u201999","author":"S. Chari","year":"1999","unstructured":"Chari, S., Jutla, C.S., Rao, J.R., et al.: Towards sound approaches to counteract power analysis attacks. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol.\u00a01666, pp. 398\u2013412. Springer, Heidelberg (1999)"},{"key":"14_CR19","unstructured":"Research Center for Information Security (RCIS) of AIST: Side-channel Attack Standard Evaluation Board (SASEBO), http:\/\/www.rcis.aist.go.jp\/special\/SASEBO\/index-en.html"},{"key":"14_CR20","unstructured":"Computer Structures Laboratory of Tohoku University.: Cryptographic Hardware Project, http:\/\/www.aoki.ecei.tohoku.ac.jp\/crypto"},{"key":"14_CR21","doi-asserted-by":"crossref","unstructured":"Qian, G., Zhou, Y., Xing, Y., et al.: A Weighted Statistical Analysis of DPA Attack on an ASIC AES Implementation. In: Proceedings of IEEE 8th International Conference on ASIC (ASICON 2009), Changsha, China, October 20-23 (2009)","DOI":"10.1109\/ASICON.2009.5351546"}],"container-title":["Lecture Notes in Computer Science","Information Security Applications"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-17955-6_14","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T21:16:05Z","timestamp":1740863765000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-17955-6_14"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642179549","9783642179556"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-17955-6_14","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011]]}}}