{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T12:04:09Z","timestamp":1743077049608,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642191367"},{"type":"electronic","value":"9783642191374"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-19137-4_7","type":"book-chapter","created":{"date-parts":[[2011,2,14]],"date-time":"2011-02-14T00:19:22Z","timestamp":1297642762000},"page":"74-85","source":"Crossref","is-referenced-by-count":1,"title":["Emulating Transactional Memory on FPGA Multiprocessors"],"prefix":"10.1007","author":[{"given":"Matteo","family":"Pusceddu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Simone","family":"Ceccolini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonino","family":"Tumeo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gianluca","family":"Palermo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donatella","family":"Sciuto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"7_CR1","unstructured":"Research Accelerator for Multiple Processors (RAMP), \n                    \n                      http:\/\/ramp.eecs.berkeley.edu\/"},{"key":"7_CR2","unstructured":"Dragojevic, V.G.A., Felber, P., Guerraoui, R.: Why STM can be more than a Research Toy. Technical report, EPFL (2009)"},{"key":"7_CR3","doi-asserted-by":"crossref","unstructured":"Arnold, J.M., Buell, D.A., Davis, E.G.: Splash 2. In: SPAA 1992: ACM Symposium on Parallel Algorithms and Architectures, pp. 316\u2013322 (1992)","DOI":"10.1145\/140901.141896"},{"issue":"3","key":"7_CR4","doi-asserted-by":"publisher","first-page":"115","DOI":"10.1145\/1394608.1382132","volume":"36","author":"L. Baugh","year":"2008","unstructured":"Baugh, L., Neelakantam, N., Zilles, C.: Using hardware memory protection to build a high-performance, strongly-atomic hybrid transactional memory. SIGARCH Comput. Archit. News\u00a036(3), 115\u2013126 (2008)","journal-title":"SIGARCH Comput. Archit. News"},{"key":"7_CR5","doi-asserted-by":"crossref","unstructured":"Grinberg, S., Weiss, S.: Investigation of transactional memory using fpgas. In: IEEE 24th Convention of Electrical and Electronics Engineers in Israel, pp. 119\u2013122 (2006)","DOI":"10.1109\/EEEI.2006.321125"},{"key":"7_CR6","doi-asserted-by":"publisher","first-page":"92","DOI":"10.1109\/MM.2004.91","volume":"24","author":"L. Hammond","year":"2004","unstructured":"Hammond, L., Carlstrom, B.D., Wong, V., Chen, M., Kozyrakis, C., Olukotun, K.: Transactional coherence and consistency: Simplifying parallel hardware and software. IEEE Micro\u00a024, 92\u2013103 (2004)","journal-title":"IEEE Micro"},{"issue":"2","key":"7_CR7","doi-asserted-by":"publisher","first-page":"289","DOI":"10.1145\/173682.165164","volume":"21","author":"M. Herlihy","year":"1993","unstructured":"Herlihy, M., Moss, J.E.B.: Transactional memory: architectural support for lock-free data structures. SIGARCH Comput. Archit. News\u00a021(2), 289\u2013300 (1993)","journal-title":"SIGARCH Comput. Archit. News"},{"key":"7_CR8","doi-asserted-by":"crossref","unstructured":"Kachris, C., Kulkarni, C.: Configurable transactional memory. In: FCCM 2007: IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 65\u201372 (2007)","DOI":"10.1109\/FCCM.2007.41"},{"key":"7_CR9","doi-asserted-by":"crossref","unstructured":"Njoroge, N., Casper, J., Wee, S., Teslyar, Y., Ge, D., Kozyrakis, C., Olukotun, K.: Atlas: a chip-multiprocessor with transactional memory support. In: DATE 2007: Design, Automation and Test in Europe, pp. 3\u20138 (2007)","DOI":"10.1109\/DATE.2007.364558"},{"key":"7_CR10","doi-asserted-by":"crossref","unstructured":"Rajwar, R., Goodman, J.R.: Transactional lock-free execution of lock-based programs. In: ASPLOS-X: Architectural Support for Programming Languages and Operating Systems, pp. 5\u201317 (2002)","DOI":"10.1145\/605432.605399"},{"key":"7_CR11","doi-asserted-by":"crossref","unstructured":"Shavit, N., Touitou, D.: Software transactional memory. In: PODC 1995: ACM Symposium on Principles of Distributed Computing, pp. 204\u2013213 (1995)","DOI":"10.1145\/224964.224987"},{"key":"7_CR12","doi-asserted-by":"crossref","unstructured":"Tumeo, A., Pilato, C., Palermo, G., Ferrandi, F., Sciuto, D.: HW\/SW methodologies for synchronization in FPGA multiprocessors. In: FPGA 2009: ACM\/SIGDA Symposium on Field Programmable Gate Arrays, pp. 265\u2013268 (2009)","DOI":"10.1145\/1508128.1508174"}],"container-title":["Lecture Notes in Computer Science","Architecture of Computing Systems - ARCS 2011"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-19137-4_7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,21]],"date-time":"2019-05-21T03:41:40Z","timestamp":1558410100000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-19137-4_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642191367","9783642191374"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-19137-4_7","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}