{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T16:45:34Z","timestamp":1773765934228,"version":"3.50.1"},"publisher-location":"Berlin, Heidelberg","reference-count":21,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783642193279","type":"print"},{"value":"9783642193286","type":"electronic"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-19328-6_1","type":"book-chapter","created":{"date-parts":[[2011,2,18]],"date-time":"2011-02-18T10:22:33Z","timestamp":1298024553000},"page":"1-25","source":"Crossref","is-referenced-by-count":128,"title":["Exascale Computing Technology Challenges"],"prefix":"10.1007","author":[{"given":"John","family":"Shalf","sequence":"first","affiliation":[]},{"given":"Sudip","family":"Dosanjh","sequence":"additional","affiliation":[]},{"given":"John","family":"Morrison","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"1_CR1","unstructured":"DOE E3 Report, \n                    \n                      http:\/\/www.er.doe.gov\/ascr\/ProgramDocuments\/ProgDocs.html"},{"key":"1_CR2","unstructured":"A Platform Strategy for the Advanced Simulation and Computing Program (NA-ASC-113R-07-Vol. 1-Rev. 0)"},{"key":"1_CR3","unstructured":"DARPA Exascale Computing Study (TR-2008-13), \n                    \n                      http:\/\/www.cse.nd.edu\/Reports\/2008\/TR-2008-13.pdf"},{"issue":"1","key":"1_CR4","doi-asserted-by":"publisher","first-page":"42","DOI":"10.1006\/jpdc.1996.1285","volume":"41","author":"D.A. Miller","year":"1997","unstructured":"Miller, D.A., Ozaktas, H.M.: Limit to the bit-rate capacity of electrical interconnects from the aspect ratio of the system architecture. J. Parallel Distrib. Comput.\u00a041(1), 42\u201352 (1997), DOI \n                    \n                      http:\/\/dx.doi.org\/10.1006\/jpdc.1996.1285","journal-title":"J. Parallel Distrib. Comput."},{"key":"1_CR5","doi-asserted-by":"crossref","unstructured":"Miller, D.A.B.: Rationale and challenges for optical interconnects to electronic chips. Proc. IEEE, 728\u2013749 (2000)","DOI":"10.1109\/5.867687"},{"issue":"1","key":"1_CR6","doi-asserted-by":"publisher","first-page":"12","DOI":"10.1109\/40.653013","volume":"18","author":"M. Horowitz","year":"1998","unstructured":"Horowitz, M., Yang, C.K.K., Sidiropoulos, S.: High-speed electrical signaling: Overview and limitations. IEEE Micro.\u00a018(1), 12\u201324 (1998)","journal-title":"IEEE Micro."},{"key":"1_CR7","unstructured":"IAA Interconnection Network Workshop, San Jose, California, July 21-22 (2008), \n                    \n                      http:\/\/www.csm.ornl.gov\/workshops\/IAA-IC-Workshop-08\/"},{"key":"1_CR8","unstructured":"Architectures and Technology for Extrame Scale Computing Workshop, San Diego, California, December 8-10 (2009), \n                    \n                      http:\/\/extremecomputing.labworks.org\/hardware\/index.stm"},{"key":"1_CR9","unstructured":"Asanovic, K., et al.: The Landscape of Parallel Computing Research: A View from Berkeley, Electrical Engineering and Computer Sciences. University of California at Berkeley, Technical Report No. UCB\/EECS-2006-183, December 18 (2006)"},{"issue":"3","key":"1_CR10","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1360612.1360617","volume":"27","author":"L. Seiler","year":"2008","unstructured":"Seiler, L., Carmean, D., Sprangle, E., Forsyth, T., Abrash, M., Dubey, P., Junkins, S., Lake, A., Sugerman, J., Cavin, R., Espasa, R., Grochowski, E., Juan, T., Hanrahan, P.: Larrabee: a many-core x86 architecture for visual computing. ACM Trans. Graph.\u00a027(3), 1\u201315 (2008)","journal-title":"ACM Trans. Graph."},{"issue":"11","key":"1_CR11","doi-asserted-by":"publisher","first-page":"943","DOI":"10.1002\/spe.952","volume":"40","author":"Y. Liu","year":"2010","unstructured":"Liu, Y., Zhu, H.: A survey of the research on power management techniques for high-performance systems. Softw. Pract. Exper.\u00a040(11), 943\u2013964 (2010)","journal-title":"Softw. Pract. Exper."},{"key":"1_CR12","unstructured":"Colmenares, J.A., Bird, S., Cook, H., Pearce, P., Zhu, D., Shalf, J., Hofmeyr, S., Asanovi\u0107, K., Kubiatowicz, J.: Resource Management in the Tesselation Manycore OS. In: HotPar 2010, Berkeley (2010), \n                    \n                      http:\/\/www.usenix.org\/event\/hotpar10\/final_posters\/Colmenares.pdf"},{"key":"1_CR13","unstructured":"U.S. Department of Energy, DOE Data Center Energy Efficiency Program (April 2009)"},{"key":"1_CR14","doi-asserted-by":"crossref","unstructured":"Moody, A., Bronevetsky, G., Mohror, K., de Supinski, B.R.: Design, Modeling, and Evaluation of a Scalable Multi-level Checkpointing System. In: IEEE\/ACM Supercomputing Conference (SC) (November 2010)","DOI":"10.2172\/984082"},{"key":"1_CR15","doi-asserted-by":"crossref","unstructured":"Kamil, S., Oliker, L., Pinar, A., Shalf, J.: Communication Requirements and Interconnect Optimization for High-End Scientific Applications. IEEE Transactions on Parallel and Distributed Systems (2009)","DOI":"10.1109\/TPDS.2009.61"},{"key":"1_CR16","first-page":"187","volume-title":"Proceedings of the 20th Annual International Conference on Supercomputing, ICS 2006","author":"J. Balfour","year":"2006","unstructured":"Balfour, J., Dally, W.J.: Design tradeoffs for tiled CMP on-chip networks. In: Proceedings of the 20th Annual International Conference on Supercomputing, ICS 2006, Cairns, Queensland, Australia, June 28-July 01, pp. 187\u2013198. ACM, New York (2006)"},{"issue":"1","key":"1_CR17","doi-asserted-by":"publisher","first-page":"33","DOI":"10.1109\/MM.2009.5","volume":"29","author":"J. Kim","year":"2009","unstructured":"Kim, J., Dally, W., Scott, S., Abts, D.: Cost-Efficient Dragonfly Topology for Large-Scale Systems. IEEE Micro.\u00a029(1), 33\u201340 (2009)","journal-title":"IEEE Micro."},{"key":"1_CR18","unstructured":"Top500 List Home, \n                    \n                      http:\/\/www.top500.org\/"},{"key":"1_CR19","volume-title":"Engineering Electromagnetics","author":"W.H. Hayt","year":"2006","unstructured":"Hayt, W.H.: Engineering Electromagnetics, 7th edn. McGraw Hill, New York (2006)","edition":"7"},{"key":"1_CR20","doi-asserted-by":"crossref","unstructured":"Guha, B., Kyotoku, B.B.C., Lipson, M.: CMOS-compatible athermal silicon microring resonators. Optics Express\u00a018(4) (2010)","DOI":"10.1364\/OE.18.003487"},{"key":"1_CR21","doi-asserted-by":"crossref","unstructured":"Hendry, G., Chan, J., Kamil, S., Oliker, L., Shalf, J., Carloni, L.P., Bergman, K.: Silicon Nanophotonic Network-On-Chip Using TDM Arbitration. In: IEEE Symposium on High Performance Interconnects (HOTI) 5.1 (August 2010)","DOI":"10.1109\/HOTI.2010.12"}],"container-title":["Lecture Notes in Computer Science","High Performance Computing for Computational Science \u2013 VECPAR 2010"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-19328-6_1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,21]],"date-time":"2019-05-21T04:09:47Z","timestamp":1558411787000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-19328-6_1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642193279","9783642193286"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-19328-6_1","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011]]}}}