{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,15]],"date-time":"2024-09-15T14:16:55Z","timestamp":1726409815557},"publisher-location":"Berlin, Heidelberg","reference-count":29,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642194474"},{"type":"electronic","value":"9783642194481"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-19448-1_3","type":"book-chapter","created":{"date-parts":[[2011,2,23]],"date-time":"2011-02-23T09:59:16Z","timestamp":1298455156000},"page":"43-68","source":"Crossref","is-referenced-by-count":0,"title":["Data Layout for Cache Performance on a Multithreaded Architecture"],"prefix":"10.1007","author":[{"given":"Subhradyuti","family":"Sarkar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dean M.","family":"Tullsen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"3_CR1","doi-asserted-by":"crossref","unstructured":"Calder, B., Krintz, C., John, S., Austin, T.: Cache-conscious data placement. In: Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (1998)","DOI":"10.1145\/291069.291036"},{"key":"3_CR2","doi-asserted-by":"crossref","unstructured":"Tullsen, D.M., Eggers, S., Levy, H.M.: Simultaneous multithreading: Maximizing on-chip parallelism. In: Proceedings of the 22nd Annual International Symposium on Computer Architecture (1995)","DOI":"10.1145\/223982.224449"},{"key":"3_CR3","doi-asserted-by":"crossref","unstructured":"Tullsen, D.M., Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L.: Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In: Proceedings of the 23rd Annual International Symposium on Computer Architecture (1996)","DOI":"10.1145\/232973.232993"},{"key":"3_CR4","doi-asserted-by":"crossref","unstructured":"Li, Y., Brooks, D., Hu, Z., Skadron, K., Bose, P.: Understanding the energy efficiency of simultaneous multithreading. In: Intl Symposium on Low Power Electronics and Design (2004)","DOI":"10.1145\/1013235.1013251"},{"key":"3_CR5","unstructured":"Seng, J., Tullsen, D., Cai, G.: Power-sensitive multithreaded architecture. In: International Conference on Computer Design (September 2000)"},{"key":"3_CR6","unstructured":"Kumar, R., Jouppi, N., Tullsen, D.M.: Conjoined-core chip multiprocessing. In: 37th International Symposium on Microarchitecture (December 2004)"},{"key":"3_CR7","unstructured":"Dolbeau, R., Seznec, A.: Cash: Revisiting hardware sharing in single-chip parallel processor. In: IRISA Report 1491 (November 2002)"},{"key":"3_CR8","doi-asserted-by":"crossref","unstructured":"Agarwal, A., Pudar, S.: Column-associative caches: A technique for reducing the miss rate of direct-mapped caches. In: International Symposium on Computer Architecture (1993)","DOI":"10.1145\/165123.165153"},{"key":"3_CR9","doi-asserted-by":"crossref","unstructured":"Topham, N., Gonz\u00e1lez, A.: Randomized cache placement for eliminating conflicts. IEEE Transactions on Computer\u00a048(2) (1999)","DOI":"10.1109\/12.752660"},{"key":"3_CR10","doi-asserted-by":"crossref","unstructured":"Seznec, A., Bodin, F.: Skewed-associative caches. In: International Conference on Parallel Architectures and Languages, pp. 305\u2013316 (1993)","DOI":"10.1007\/3-540-56891-3_24"},{"key":"3_CR11","unstructured":"Lynch, W.L., Bray, B.K., Flynn, M.J.: The effect of page allocation on caches. In: 25th Annual International Symposium on Microarchitecture (1992)"},{"key":"3_CR12","doi-asserted-by":"crossref","unstructured":"Rivera, G., Tseng, C.W.: Data transformations for eliminating conflict misses. In: SIGPLAN Conference on Programming Language Design and Implementation, pp. 38\u201349 (1998)","DOI":"10.1145\/277652.277661"},{"key":"3_CR13","doi-asserted-by":"crossref","unstructured":"Mueller, F.: Compiler support for software-based cache partitioning. In: Workshop on Languages, Compilers and Tools for Real-Time Systems, pp. 125\u2013133 (1995)","DOI":"10.1145\/216633.216677"},{"key":"3_CR14","unstructured":"Juan, T., Royo, D.: Dynamic cache splitting. In: XV International Confernce of the Chilean Computational Society (1995)"},{"key":"3_CR15","doi-asserted-by":"crossref","unstructured":"Bershad, B.N., Lee, D., Romer, T.H., Chen, J.B.: Avoiding conflict misses dynamically in large direct-mapped caches. In: Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, USA, October 5\u20137, pp. 158\u2013170 (1994)","DOI":"10.1145\/195473.195527"},{"key":"3_CR16","doi-asserted-by":"crossref","unstructured":"Sherwood, T., Calder, B., Emer, J.S.: Reducing cache misses using hardware and software page placement. In: International Conference on Supercomputing, pp. 155\u2013164 (1999)","DOI":"10.1145\/305138.305189"},{"key":"3_CR17","unstructured":"Nemirovsky, M., Yamamoto, W.: Quantitative study on data caches on a multistreamed architecture. In: Workshop on Multithreaded Execution, Architecture and Compilation (1998)"},{"key":"3_CR18","unstructured":"Hily, S., Seznec, A.: Standard memory hierarchy does not fit simultaneous multithreading. In: Proceedings of the Workshop on Multithreaded Execution Architecture and Compilation, with HPCA-4 (1998)"},{"key":"3_CR19","unstructured":"Jos, M.G.: Data caches for multithreaded processors. In: Workshop on Multithreaded Execution, Architecture and Compilation (2000)"},{"key":"3_CR20","first-page":"145","volume-title":"Communicating Process Architectures","author":"D. May","year":"2000","unstructured":"May, D., Irwin, J., Muller, H.L., Page, D.: Effective caching for multithreaded processors. In: Communicating Process Architectures, pp. 145\u2013154. IOS Press, Amsterdam (2000)"},{"key":"3_CR21","doi-asserted-by":"crossref","unstructured":"Nikolopoulos, D.S.: Code and data transformations for improving shared cache performance on SMT processors. In: International Symposium on High Performance Computing, pp. 54\u201369 (2003)","DOI":"10.1007\/978-3-540-39707-6_5"},{"key":"3_CR22","doi-asserted-by":"crossref","unstructured":"Lopez, S., Dropsho, S., Albonesi, D.H., Garnica, O., Lanchares, J.: Dynamic capacity-speed tradeoffs in smt processor caches. In: Intl Conference on High Performance Embedded Architectures & Compilers (January 2007)","DOI":"10.1007\/978-3-540-69338-3_10"},{"key":"3_CR23","unstructured":"Kumar, R., Tullsen, D.M.: Compiling for instruction cache performance on a multithreaded architecture. In: 35th Annual International Symposium on Microarchitecture (2002)"},{"key":"3_CR24","unstructured":"Sarkar, S., Tullsen, D.M.: Compiler techniques for reducing data cache miss rate on a multithreaded architecture. In: Proceedings of the International Conference on High Performance Embedded Architectures and Compilers (2008)"},{"key":"3_CR25","unstructured":"Tullsen, D.M.: Simulation and modeling of a simultaneous multithreading processor. In: 22nd Annual Computer Measurement Group Conference (December 1996)"},{"key":"3_CR26","unstructured":"Tullsen, D.M., Brown, J.: Handling long-latency loads in a simultaneous multithreaded processor. In: 34th International Symposium on Microarchitecture (December 2001)"},{"key":"3_CR27","doi-asserted-by":"publisher","first-page":"528","DOI":"10.1145\/989393.989446","volume":"39","author":"A. Srivastava","year":"2004","unstructured":"Srivastava, A., Eustace, A.: Atom: a system for building customized program analysis tools. SIGPLAN Notices\u00a039, 528\u2013539 (2004)","journal-title":"SIGPLAN Notices"},{"key":"3_CR28","doi-asserted-by":"crossref","unstructured":"Grunwald, D., Zorn, B.G., Henderson, R.: Improving the cache locality of memory allocation. In: SIGPLAN Conference on Programming Language Design and Implementation (1993)","DOI":"10.1145\/155090.155107"},{"key":"3_CR29","doi-asserted-by":"crossref","unstructured":"Robson, J.M.: Worst case fragmentation of first fit and best fit storage allocation strategies. The Computer Journal\u00a020(3) (1977)","DOI":"10.1093\/comjnl\/20.3.242"}],"container-title":["Lecture Notes in Computer Science","Transactions on High-Performance Embedded Architectures and Compilers III"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-19448-1_3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,21]],"date-time":"2019-05-21T08:56:14Z","timestamp":1558428974000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-19448-1_3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642194474","9783642194481"],"references-count":29,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-19448-1_3","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}