{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,3]],"date-time":"2025-03-03T05:55:57Z","timestamp":1740981357372,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642194474"},{"type":"electronic","value":"9783642194481"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-19448-1_8","type":"book-chapter","created":{"date-parts":[[2011,2,23]],"date-time":"2011-02-23T09:59:16Z","timestamp":1298455156000},"page":"135-153","source":"Crossref","is-referenced-by-count":12,"title":["Power-Aware Dynamic Cache Partitioning for CMPs"],"prefix":"10.1007","author":[{"given":"Isao","family":"Kotera","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kenta","family":"Abe","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryusuke","family":"Egawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroyuki","family":"Takizawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroaki","family":"Kobayashi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"2","key":"8_CR1","doi-asserted-by":"publisher","first-page":"176","DOI":"10.1145\/106975.106991","volume":"19","author":"D.W. Wall","year":"1991","unstructured":"Wall, D.W.: Limits of instruction-level parallelism. SIGARCH Comput. Archit. News\u00a019(2), 176\u2013188 (1991)","journal-title":"SIGARCH Comput. Archit. News"},{"issue":"9","key":"8_CR2","doi-asserted-by":"publisher","first-page":"79","DOI":"10.1109\/2.612253","volume":"30","author":"B. Nayfeh","year":"1997","unstructured":"Nayfeh, B., Olukotun, K.: A single-chip multiprocessor. Computer\u00a030(9), 79\u201385 (1997)","journal-title":"Computer"},{"issue":"1","key":"8_CR3","doi-asserted-by":"publisher","first-page":"7","DOI":"10.1023\/B:SUPE.0000014800.27383.8f","volume":"28","author":"G.E. Suh","year":"2004","unstructured":"Suh, G.E., Rudolph, L., Devadas, S.: Dynamic partitioning of shared cache memory. Journal of Supercomputing\u00a028(1), 7\u201326 (2004)","journal-title":"Journal of Supercomputing"},{"key":"8_CR4","first-page":"340","volume-title":"HPCA 2005: Proceedings of the 11th International Symposium on High-Performance Computer Architecture","author":"D. Chandra","year":"2005","unstructured":"Chandra, D., Guo, F., Kim, S., Solihin, Y.: Predicting inter-thread cache contention on a chip multi-processor architecture. In: HPCA 2005: Proceedings of the 11th International Symposium on High-Performance Computer Architecture, Washington, DC, USA, pp. 340\u2013351. IEEE Computer Society, Los Alamitos (2005)"},{"key":"8_CR5","first-page":"111","volume-title":"PACT 2004: the 13th International Conference on Parallel Architectures and Compilation Techniques","author":"S. Kim","year":"2004","unstructured":"Kim, S., Chandra, D., Solihin, Y.: Fair cache sharing and partitioning in a chip multiprocessor architecture. In: PACT 2004: the 13th International Conference on Parallel Architectures and Compilation Techniques, Washington, DC, USA, pp. 111\u2013122. IEEE Computer Society, Los Alamitos (2004)"},{"key":"8_CR6","first-page":"423","volume-title":"MICRO 39: the 39th Annual IEEE\/ACM International Symposium on Microarchitecture","author":"M.K. Qureshi","year":"2006","unstructured":"Qureshi, M.K., Patt, Y.N.: Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In: MICRO 39: the 39th Annual IEEE\/ACM International Symposium on Microarchitecture, Washington, DC, USA, pp. 423\u2013432. IEEE Computer Society, Los Alamitos (2006)"},{"key":"8_CR7","doi-asserted-by":"crossref","unstructured":"Butts, J.A., Sohi, G.: A static power model for architects. In: MICRO-33: 33rd Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 191\u2013201 (2000)","DOI":"10.1145\/360128.360148"},{"issue":"12","key":"8_CR8","doi-asserted-by":"publisher","first-page":"68","DOI":"10.1109\/MC.2003.1250885","volume":"36","author":"N. Kim","year":"2003","unstructured":"Kim, N., Austin, T., Blaauw, D., Mudge, T., Flautner, K., Hu, J., Irwin, M., Kandemir, M., Narayanan, V.: Leakage current: Moore\u2019s law meets static power. Computer\u00a036(12), 68\u201375 (2003)","journal-title":"Computer"},{"key":"8_CR9","unstructured":"International technology roadmap for semiconductors, http:\/\/public.itrs.net"},{"issue":"3","key":"8_CR10","doi-asserted-by":"publisher","first-page":"221","DOI":"10.1145\/1089008.1089009","volume":"2","author":"Y. Meng","year":"2005","unstructured":"Meng, Y., Sherwood, T., Kastner, R.: Exploring the limits of leakage power reduction in caches. ACM Trans. Archit. Code Optim.\u00a02(3), 221\u2013246 (2005)","journal-title":"ACM Trans. Archit. Code Optim."},{"issue":"12","key":"8_CR11","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1109\/MC.2003.1250876","volume":"36","author":"M. Stan","year":"2003","unstructured":"Stan, M., Skadron, K.: Power-aware computing. Computer\u00a036(12), 35\u201338 (2003)","journal-title":"Computer"},{"key":"8_CR12","doi-asserted-by":"crossref","unstructured":"Albonesi, D.: Selective cache ways: on-demand cache resource allocation. In: MICRO-32: 32nd Annual International Symposium on Microarchitecture, pp. 248\u2013259 (November 1999)","DOI":"10.1109\/MICRO.1999.809463"},{"issue":"1","key":"8_CR13","doi-asserted-by":"publisher","first-page":"77","DOI":"10.1109\/92.920821","volume":"9","author":"M. Powell","year":"2001","unstructured":"Powell, M., Yang, S.H., Falsafi, B., Roy, K., Vijaykumar, N.: Reducing leakage in a high-performance deep-submicron instruction cache. IEEE Transactions on Very Large Scale Integration (VLSI) Systems\u00a09(1), 77\u201389 (2001)","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"8_CR14","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1109\/LPE.2000.876763","volume-title":"ISLPED 2000: The 2000 International Symposium on Low Power Electronics and Design","author":"M. Powell","year":"2000","unstructured":"Powell, M., Yang, S.H., Falsafi, B., Roy, K., Vijaykumar, T.N.: Gated-vdd: a circuit technique to reduce leakage in deep-submicron cache memories. In: ISLPED 2000: The 2000 International Symposium on Low Power Electronics and Design, pp. 90\u201395. ACM, New York (2000)"},{"key":"8_CR15","doi-asserted-by":"crossref","unstructured":"Kaxiras, S., Hu, Z., Martonosi, M.: Cache decay: exploiting generational behavior to reduce cache leakage power. In: 28th Annual International Symposium on Computer Architecture, June 30-July 4, pp. 240\u2013251 (2001)","DOI":"10.1145\/384285.379268"},{"key":"8_CR16","doi-asserted-by":"crossref","unstructured":"Flautner, K., Kim, N.S., Martin, S., Blaauw, D., Mudge, T.: Drowsy caches: simple techniques for reducing leakage power. In: 29th Annual International Symposium on Computer Architecture, May 25-29, pp. 148\u2013157 (2002)","DOI":"10.1145\/545214.545232"},{"issue":"3","key":"8_CR17","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1145\/1101868.1101874","volume":"33","author":"H. Kobayashi","year":"2005","unstructured":"Kobayashi, H., Kotera, I., Takizawa, H.: Locality analysis to control dynamically way-adaptable caches. SIGARCH Comput. Archit. News\u00a033(3), 25\u201332 (2005)","journal-title":"SIGARCH Comput. Archit. News"},{"issue":"4","key":"8_CR18","doi-asserted-by":"publisher","first-page":"52","DOI":"10.1109\/MM.2006.82","volume":"26","author":"N. Binkert","year":"2006","unstructured":"Binkert, N., Dreslinski, R., Hsu, L., Lim, K., Saidi, A., Reinhardt, S.: The m5 simulator: Modeling networked systems. IEEE Micro\u00a026(4), 52\u201360 (2006)","journal-title":"IEEE Micro"},{"issue":"5","key":"8_CR19","doi-asserted-by":"publisher","first-page":"677","DOI":"10.1109\/4.509850","volume":"31","author":"S. Wilton","year":"1996","unstructured":"Wilton, S., Jouppi, N.: Cacti: an enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits\u00a031(5), 677\u2013688 (1996)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"8_CR20","unstructured":"The Standard Performance Evaluation Corporation, http:\/\/www.spec.org\/"}],"container-title":["Lecture Notes in Computer Science","Transactions on High-Performance Embedded Architectures and Compilers III"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-19448-1_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,2]],"date-time":"2025-03-02T22:47:01Z","timestamp":1740955621000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-19448-1_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642194474","9783642194481"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-19448-1_8","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}