{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:01:38Z","timestamp":1761580898157,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642218774"},{"type":"electronic","value":"9783642218781"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-21878-1_12","type":"book-chapter","created":{"date-parts":[[2011,7,13]],"date-time":"2011-07-13T11:10:15Z","timestamp":1310555415000},"page":"87-97","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs"],"prefix":"10.1007","author":[{"given":"Alberto","family":"Ros","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel E.","family":"Acacio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"12_CR1","doi-asserted-by":"crossref","unstructured":"Borkar, S.: Thousand core chips: A technology perspective. In: 44th Annual Design Automation Conference, pp. 746\u2013749 (2007)","DOI":"10.1145\/1278480.1278667"},{"key":"12_CR2","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1109\/MM.2002.997877","volume":"22","author":"M.B. Taylor","year":"2002","unstructured":"Taylor, M.B., Kim, J., Miller, J., et al.: The raw microprocessor: A computational fabric for software circuits and general purpose programs. IEEE Micro\u00a022, 25\u201335 (2002)","journal-title":"IEEE Micro"},{"key":"12_CR3","doi-asserted-by":"crossref","unstructured":"Zhang, M., Asanovi\u0107, K.: Victim replication: Maximizing capacity while hiding wire delay in tiled chip multiprocessors. In: 32nd Int\u2019l Symp. on Computer Architecture (ISCA), pp. 336\u2013345 (2005)","DOI":"10.1145\/1080695.1069998"},{"key":"12_CR4","unstructured":"Intel Res.: Single-chip Cloud Computer (2010), http:\/\/techresearch.intel.com\/articles\/Tera-Scale\/1826.htm"},{"key":"12_CR5","doi-asserted-by":"crossref","unstructured":"Leverich, J., Arakida, H., Solomatnikov, A., Firoozshahian, A., Horowitz, M., Kozyrakis, C.: Comparing memory systems for chip multiprocessors. In: 34th Int\u2019l Symp. on Computer Architecture (ISCA), pp. 358\u2013368 (2007)","DOI":"10.1145\/1250662.1250707"},{"key":"12_CR6","doi-asserted-by":"crossref","unstructured":"Acacio, M.E., Gonz\u00e1lez, J., Garc\u00eda, J.M., Duato, J.: A new scalable directory architecture for large-scale multiprocessors. In: 7th Int\u2019l Symp. on High-Performance Computer Architecture (HPCA), pp. 97\u2013106 (2001)","DOI":"10.1109\/HPCA.2001.903255"},{"key":"12_CR7","doi-asserted-by":"crossref","unstructured":"Rodrigo, S., Flich, J., Duato, J., Hummel, M.: Efficient unicast and multicast support for CMPs. In: 41st IEEE\/ACM Int\u2019l Symp. on Microarchitecture (MICRO), pp. 364\u2013375 (2008)","DOI":"10.1109\/MICRO.2008.4771805"},{"key":"12_CR8","doi-asserted-by":"crossref","unstructured":"Kim, C., Burger, D., Keckler, S.W.: An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. In: 10th Int. Conf. on Architectural Support for Programming Language and Operating Systems (ASPLOS), pp. 211\u2013222 (2002)","DOI":"10.1145\/605432.605420"},{"key":"12_CR9","doi-asserted-by":"publisher","first-page":"50","DOI":"10.1109\/2.982916","volume":"35","author":"P.S. Magnusson","year":"2002","unstructured":"Magnusson, P.S., Christensson, M., Eskilson, J., et al.: Simics: A full system simulation platform. IEEE Computer\u00a035, 50\u201358 (2002)","journal-title":"IEEE Computer"},{"key":"12_CR10","doi-asserted-by":"publisher","first-page":"92","DOI":"10.1145\/1105734.1105747","volume":"33","author":"M.M. Martin","year":"2005","unstructured":"Martin, M.M., Sorin, D.J., Beckmann, B.M., et al.: Multifacet\u2019s general execution-driven multiprocessor simulator (GEMS) toolset. Computer Architecture News\u00a033, 92\u201399 (2005)","journal-title":"Computer Architecture News"},{"key":"12_CR11","doi-asserted-by":"crossref","unstructured":"Puente, V., Gregorio, J.A., Beivide, R.: SICOSYS: An integrated framework for studying interconnection network in multiprocessor systems. In: 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing, pp. 15\u201322 (2002)","DOI":"10.1109\/EMPDP.2002.994207"},{"key":"12_CR12","unstructured":"Thoziyoor, S., Muralimanohar, N., Ahn, J.H., Jouppi, N.P.: CACTI 5.1. Technical Report HPL-2008-20, HP Labs (2008)"},{"key":"12_CR13","doi-asserted-by":"publisher","first-page":"73","DOI":"10.1109\/40.768506","volume":"19","author":"T. Horel","year":"1999","unstructured":"Horel, T., Lauterbach, G.: UltraSPARC-III: Designing third-generation 64-bit performance. IEEE Micro\u00a019, 73\u201385 (1999)","journal-title":"IEEE Micro"},{"key":"12_CR14","doi-asserted-by":"crossref","unstructured":"Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The SPLASH-2 programs: Characterization and methodological considerations. In: 22nd Int\u2019l Symp. on Computer Architecture (ISCA), pp. 24\u201336 (1995)","DOI":"10.1145\/225830.223990"},{"key":"12_CR15","unstructured":"Li, M.L., Sasanka, R., Adve, S.V., Chen, Y.K., Debes, E.: The ALPBench benchmark suite for complex multimedia applications. In: Int\u2019l Symp. on Workload Characterization, pp. 34\u201345 (2005)"},{"key":"12_CR16","unstructured":"Wang, H., Peh, L.S., Malik, S.: Power-driven design of router microarchitectures in on-chip networks. In: 36th IEEE\/ACM Int\u2019l Symp. on Microarchitecture (MICRO), pp. 105\u2013111 (2003)"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2010 Parallel Processing Workshops"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-21878-1_12","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,7]],"date-time":"2025-03-07T02:28:45Z","timestamp":1741314525000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-21878-1_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642218774","9783642218781"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-21878-1_12","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]},"assertion":[{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}