{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,10]],"date-time":"2025-11-10T08:41:45Z","timestamp":1762764105106,"version":"build-2065373602"},"publisher-location":"Berlin, Heidelberg","reference-count":21,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642218866"},{"type":"electronic","value":"9783642218873"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-21887-3_36","type":"book-chapter","created":{"date-parts":[[2011,6,17]],"date-time":"2011-06-17T13:51:08Z","timestamp":1308318668000},"page":"463-474","source":"Crossref","is-referenced-by-count":0,"title":["Thermal-Aware Floorplan Schemes for Reliable 3D Multi-core Processors"],"prefix":"10.1007","author":[{"given":"Dong Oh","family":"Son","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Young Jin","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jin Woo","family":"Ahn","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jae Hyung","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jong Myon","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cheol Hong","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"36_CR1","unstructured":"Joyner, J.W., Zarkesh-Ha, P., Davis, J.A., Meindl, J.D.: A Three-Dimensional Stochastic Wire-Length Distribution for Variable Separation of Strata. In: Proc. of IEEE International Interconnect Technology Conference, San Francisco, pp. 132\u2013134 (2000)"},{"key":"36_CR2","doi-asserted-by":"crossref","unstructured":"Jang, H.B., Yoon, I., Kim, C.H., Shin, S., Chung, S.W.: The impact of liquid cooling on 3D multi-core processors. In: Proc. of the 2009 IEEE International Conference on Computer Design, California, pp. 472\u2013478 (2009)","DOI":"10.1109\/ICCD.2009.5413115"},{"issue":"8","key":"36_CR3","doi-asserted-by":"publisher","first-page":"1479","DOI":"10.1109\/TCAD.2008.925793","volume":"27","author":"C. Zhu","year":"2008","unstructured":"Zhu, C., Gu, Z., Shang, L., Dick, R.P., Joseph, R.: Three-dimensional chip-multiprocessor run-time thermal management. IEEE Transactions on Computer-Aided Design of Lntegrated Circuits and Systems\u00a027(8), 1479\u20131492 (2008)","journal-title":"IEEE Transactions on Computer-Aided Design of Lntegrated Circuits and Systems"},{"key":"36_CR4","doi-asserted-by":"crossref","unstructured":"Yoon, S.W., Yang, D.W., Koo, J.H., Padmanathan, M., Carson, F.: 3D TSV processes and its assembly\/packaging technology. In: Proc. of the IEEE International Conference on 3D System Integration, San Francisco, pp. 1\u20135 (2009)","DOI":"10.1109\/3DIC.2009.5306535"},{"key":"36_CR5","doi-asserted-by":"crossref","unstructured":"Puttaswamy, K., Loh, G.L.: Dynamic Instruction Scheduling in a 3-Dimensional Integration Technology. In: Proc. of the ACM Great Lakes Symposium On VLSI, Philadelphia, pp. 153\u2013158 (2006)","DOI":"10.1145\/1127908.1127946"},{"key":"36_CR6","doi-asserted-by":"crossref","unstructured":"Puttaswamy, K., Loh, G.H.: Implemeting Caches in a 3D Technology for High Performance Processors. In: Proc. of the Int. Conf. on Comp. Design, San Jose, pp. 525\u2013532 (2005)","DOI":"10.1109\/ICCD.2005.65"},{"key":"36_CR7","doi-asserted-by":"crossref","unstructured":"Puttaswamy, K., Loh, G.H.: Thermal Analysis of a 3D Die Stacked High Performance Microprocessor. In: Proc. of ACM Great Lakes Symposium on VLSI, Philadelphia, pp. 19\u201324 (2006)","DOI":"10.1145\/1127908.1127915"},{"key":"36_CR8","doi-asserted-by":"crossref","unstructured":"Cong, J., Luo, G.J., Wei, J., Zhang, Y.: Thermal-Aware 3D IC Placement Via Transformation. In: Proc. of ASP-DAC, Yokohama, pp. 780\u2013785 (2007)","DOI":"10.1109\/ASPDAC.2007.358084"},{"key":"36_CR9","unstructured":"Brooks, D., Martonosi, M.: Dynamic thermal management for high-performance microprocessors. In: Proc. of the 27th International Symposium on Computer Architecture, Vancouver, pp. 83\u201394 (2000)"},{"key":"36_CR10","unstructured":"Pering, T., Brodersen, R.: Energy efficient voltage scheduling for real-time operating systems. In: Proc. of the 4th IEEE Real-Time Technology and Applications Symposium RTAS 1998, Work in Progress Session, Denver (1998)"},{"key":"36_CR11","unstructured":"Mishra, R., Rastogi, N., Zhu, D., Mosse, D., Melhem, R.: Energy Aware Scheduling for Distributed Real-Time Systems. In: The Proc. International Parallel and Distributed Processing Symposium, Nice, pp. 21\u201330 (2003)"},{"key":"36_CR12","doi-asserted-by":"crossref","unstructured":"Zhou, X., Xu, Y., Du, Y., Zhang, Y., Yang, J.: Thermal Management for 3D Processors via Task Scheduling. In: Proc. of the 2008 37th International Conference on Parallel Processing, Portland, pp. 115\u2013122 (2008)","DOI":"10.1109\/ICPP.2008.51"},{"issue":"1","key":"36_CR13","doi-asserted-by":"publisher","first-page":"96","DOI":"10.1109\/TCAD.2007.907062","volume":"27","author":"A. Kumar","year":"2008","unstructured":"Kumar, A., Shang, L., Peh, L.S., Jha, N.K.: System-level dynamic thermal management for high-performance microprocessors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a027(1), 96\u2013108 (2008)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"6","key":"36_CR14","doi-asserted-by":"publisher","first-page":"1120","DOI":"10.1109\/TVLSI.2003.817546","volume":"11","author":"S.N. Adya","year":"2003","unstructured":"Adya, S.N., Markov, I.L.: Fixed-outline floorplanning: enabling hierarchical design. IEEE Trans. on Very Large Scale Integration (VLSI) Systems\u00a011(6), 1120\u20131135 (2003)","journal-title":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems"},{"key":"36_CR15","doi-asserted-by":"crossref","unstructured":"Puttaswanmy, K., Loh, G.H.: Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. In: Proc. of the 13th International Symposium on High-Performance Computer Architecture, Arizona, pp. 193\u2013204 (2007)","DOI":"10.1109\/HPCA.2007.346197"},{"key":"36_CR16","first-page":"1","volume":"7","author":"K. Sankaranarayanan","year":"2005","unstructured":"Sankaranarayanan, K., Velusamy, S., Stan, M., Skadron, K.: A Case for Thermal-Aware Flooplanning at the Microacrchitecture Level. Journal of Instruction-Level Parallelism\u00a07, 1\u201316 (2005)","journal-title":"Journal of Instruction-Level Parallelism"},{"issue":"2","key":"36_CR17","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/40.755465","volume":"19","author":"P.E. Kessler","year":"1999","unstructured":"Kessler, P.E.: The Alpha 21264 Microprocessor. IEEE Micro\u00a019(2), 24\u201336 (1999)","journal-title":"IEEE Micro"},{"issue":"3","key":"36_CR18","first-page":"13","volume":"25","author":"D.C. Burger","year":"1997","unstructured":"Burger, D.C., Austin, T.M.: The SimpleScalar tool set, version 2.0. ACM SIGARCH CAN\u00a025(3), 13\u201325 (1997)","journal-title":"ACM SIGARCH CAN"},{"key":"36_CR19","doi-asserted-by":"crossref","unstructured":"Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power analysis and optimizations. In: Proc. of the 27th International Symposium on Computer Architecture, Vancouver, pp. 83\u201394 (2000)","DOI":"10.1145\/339647.339657"},{"issue":"7","key":"36_CR20","doi-asserted-by":"publisher","first-page":"28","DOI":"10.1109\/2.869367","volume":"33","author":"J.L. Henning","year":"2000","unstructured":"Henning, J.L.: SPEC CPU2000: Measuring CPU Performance in the New Millennium. IEEE Computer\u00a033(7), 28\u201335 (2000)","journal-title":"IEEE Computer"},{"key":"36_CR21","unstructured":"Hotspot, \nhttp:\/\/lava.cs.virginia.edu\/HotSpot"}],"container-title":["Lecture Notes in Computer Science","Computational Science and Its Applications - ICCSA 2011"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-21887-3_36","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,10]],"date-time":"2025-11-10T08:37:25Z","timestamp":1762763845000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-642-21887-3_36"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642218866","9783642218873"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-21887-3_36","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}