{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T20:16:23Z","timestamp":1742933783642,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":23,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642226182"},{"type":"electronic","value":"9783642226199"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-22619-9_6","type":"book-chapter","created":{"date-parts":[[2011,8,8]],"date-time":"2011-08-08T04:45:25Z","timestamp":1312778725000},"page":"108-124","source":"Crossref","is-referenced-by-count":0,"title":["An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications"],"prefix":"10.1007","author":[{"given":"Tadayoshi","family":"Horita","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Itsuo","family":"Takanami","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"12","key":"6_CR1","doi-asserted-by":"publisher","first-page":"1297","DOI":"10.1109\/12.895848","volume":"49","author":"H. Lim","year":"2000","unstructured":"Lim, H., Piuri, V., Swartzlander, E.E.: A serial-parallel architecture for two-dimensional discrete cosine and inverse discrete cosine transforms. IEEE Trans. on Comput.\u00a049(12), 1297\u20131309 (2000)","journal-title":"IEEE Trans. on Comput."},{"issue":"4","key":"6_CR2","doi-asserted-by":"publisher","first-page":"501","DOI":"10.1109\/12.21143","volume":"38","author":"S.Y. Kung","year":"1989","unstructured":"Kung, S.Y., Jean, S.N., Chang, C.W.: Fault-tolerant array processors using single-track switches. IEEE Trans. Comput.\u00a038(4), 501\u2013514 (1989)","journal-title":"IEEE Trans. Comput."},{"issue":"9","key":"6_CR3","first-page":"1898","volume":"E81-A","author":"N. Shigei","year":"1998","unstructured":"Shigei, N., Miyajima, H.: On the search for effective spare arrangement for reconfigurable processor arrays using genetic algorithm. IEICE Trans. Fundamentals\u00a0E81-A(9), 1898\u20131901 (1998)","journal-title":"IEICE Trans. Fundamentals"},{"issue":"2","key":"6_CR4","doi-asserted-by":"publisher","first-page":"175","DOI":"10.1109\/71.663881","volume":"9","author":"G. Kim","year":"1998","unstructured":"Kim, G., Yoon, H.: On submesh allocation for mesh multicomputers: A best-fit allocation and a virtual submesh allocation for faulty meshes. IEEE Trans. Parallel and Distributed Systems\u00a09(2), 175\u2013185 (1998)","journal-title":"IEEE Trans. Parallel and Distributed Systems"},{"issue":"1","key":"6_CR5","first-page":"56","volume":"E81-D","author":"T. Yamada","year":"1998","unstructured":"Yamada, T., Ueno, S.: Fault-tolerant meshes with efficient layouts. IEICE Trans. Inf. & Syst.\u00a0E81-D(1), 56\u201365 (1998)","journal-title":"IEICE Trans. Inf. & Syst."},{"issue":"3","key":"6_CR6","doi-asserted-by":"publisher","first-page":"251","DOI":"10.1109\/24.914543","volume":"49","author":"L.E. LaForge","year":"2000","unstructured":"LaForge, L.E.: What designers of microelectronic systems should know about arrays spared by rows and columns. IEEE Trans. Reliability\u00a049(3), 251\u2013272 (2000)","journal-title":"IEEE Trans. Reliability"},{"issue":"5","key":"6_CR7","doi-asserted-by":"publisher","first-page":"553","DOI":"10.1109\/TC.2002.1004594","volume":"51","author":"L. Zhang","year":"2002","unstructured":"Zhang, L.: Fault-tolerant meshes with small degree. IEEE Trans. Comput.\u00a051(5), 553\u2013560 (2002)","journal-title":"IEEE Trans. Comput."},{"issue":"6","key":"6_CR8","doi-asserted-by":"publisher","first-page":"553","DOI":"10.1109\/12.862215","volume":"49","author":"C.P. Low","year":"2000","unstructured":"Low, C.P.: An efficient reconfiguration algorithm for degradable VLSI\/WSI arrays. IEEE Trans. Comput.\u00a049(6), 553\u2013559 (2000)","journal-title":"IEEE Trans. Comput."},{"issue":"6","key":"6_CR9","doi-asserted-by":"publisher","first-page":"542","DOI":"10.1109\/12.862214","volume":"49","author":"T. Horita","year":"2000","unstructured":"Horita, T., Takanami, I.: Fault tolerant processor arrays based on the 1 $\\frac{1}{2}$ -track switches with flexible spare distributions. IEEE Trans. Comput.\u00a049(6), 542\u2013552 (2000)","journal-title":"IEEE Trans. Comput."},{"issue":"8","key":"6_CR10","first-page":"1160","volume":"E79-D","author":"T. Horita","year":"1996","unstructured":"Horita, T., Takanami, I.: A built-in self-reconstruction approach for partitioned mesh-arrays using neural algorithm. IEICE Trans. Inf. & Syst.\u00a0E79-D(8), 1160\u20131167 (1996)","journal-title":"IEICE Trans. Inf. & Syst."},{"issue":"12","key":"6_CR11","first-page":"1801","volume":"E84-D","author":"T. Horita","year":"2001","unstructured":"Horita, T., Takanami, I.: A system for efficiently self-reconstructing 1 $\\frac{1}{2}$ -track switch torus arrays. IEICE Trans. Inf. & Syst.\u00a0E84-D(12), 1801\u20131809 (2001)","journal-title":"IEICE Trans. Inf. & Syst."},{"issue":"12","key":"6_CR12","first-page":"2743","volume":"E86-D","author":"T. Horita","year":"2003","unstructured":"Horita, T., Takanami, I.: A system for efficiently self-reconstructing array system using E-1 $\\frac{1}{2}$ -track switches. IEICE Trans. Inf. & Syst.\u00a0E86-D(12), 2743\u20132752 (2003)","journal-title":"IEICE Trans. Inf. & Syst."},{"key":"6_CR13","unstructured":"Horita, T., Takanami, I.: The total system reliabilities for fault-tolerant self-reconfigurable array systems. In: Advances in Computer Science and Engineering, vol.\u00a02(2), pp. 165\u2013187. Pushpa Publishing House (2008)"},{"key":"6_CR14","doi-asserted-by":"crossref","unstructured":"Horita, T., Yamashita, T., Takanami, I.: A reliability analysis for various fault-tolerant 2D processor arrays using 1.5-track switches. In: Advances in Computer Science and Engineering, vol.\u00a02(3), pp. 243\u2013266. Pushpa Publishing House (2008)","DOI":"10.1093\/ietfec\/e91-a.2.623"},{"issue":"2","key":"6_CR15","doi-asserted-by":"publisher","first-page":"623","DOI":"10.1093\/ietfec\/e91-a.2.623","volume":"E91-A","author":"T. Horita","year":"2008","unstructured":"Horita, T., Katou, Y., Takanami, I.: An analysis for fault-tolerant 3D processor arrays using 1.5-track switches. IEICE Trans. Fundamentals\u00a0E91-A(2), 623\u2013632 (2008)","journal-title":"IEICE Trans. Fundamentals"},{"key":"6_CR16","doi-asserted-by":"crossref","unstructured":"Bednara, M., Daldrup, M., Teich, J., von zur Gathen, J., Shokrollahi, J.: Tradeoff analysis of FPGA based elliptic curve cryptography. In: Proc. IEEE Int\u2019l Symp. on ISCAS 2002, vol.\u00a05, pp. 797\u2013800 (2002)","DOI":"10.1109\/ISCAS.2002.1010824"},{"key":"6_CR17","doi-asserted-by":"crossref","unstructured":"Ors, S.B., Batina, L., Preneel, B., Vandewalle, J.: Hardware implementation of a montgomery modular multiplier in a systolic array. In: Proc. IEEE Int\u2019l Symp. on IPDPS 2003, pp. 184\u2013192 (2003)","DOI":"10.1109\/IPDPS.2003.1213341"},{"key":"6_CR18","doi-asserted-by":"crossref","unstructured":"Wang, Y.B., Dong, X.J., Tian, Z.G.: FPGA based design of elliptic curve cryptography coprocessor. In: Proc. Int\u2019l Conf. on ICNC 2007, vol.\u00a05, pp. 185\u2013189 (2007)","DOI":"10.1109\/ICNC.2007.391"},{"issue":"2","key":"6_CR19","doi-asserted-by":"publisher","first-page":"562","DOI":"10.1093\/ietisy\/e90-d.2.562","volume":"E90-D","author":"Y. Kim","year":"2007","unstructured":"Kim, Y., Jeong, H.: A systolic FPGA architecture of two-level dynamic programming for connected speech recognition. IEICE Trans. Inf. & Syst.\u00a0E90-D(2), 562\u2013568 (2007)","journal-title":"IEICE Trans. Inf. & Syst."},{"key":"6_CR20","doi-asserted-by":"crossref","unstructured":"Fukushi, M., Horiguchi, S.: Self-reconfigurable mesh array system on FPGA. In: Proc. IEEE Intl Symp. on DFT, pp. 240\u2013248 (2000)","DOI":"10.1109\/DFTVS.2000.887162"},{"key":"6_CR21","unstructured":"Horita, T., Takanami, I.: An implementation of a fault-tolerant 2D systolic array on FPGAs and its evaluation. In: Proc. CSREA Int\u2019l Conf. on Technologies and Applications PDPTA 2009, pp. 136\u2013142 (2009)"},{"key":"6_CR22","unstructured":"Altera reliability report homepage (2009), http:\/\/www.altera.com\/literature\/rr\/rr.pdf"},{"issue":"9","key":"6_CR23","first-page":"879","volume":"E80-D","author":"T. Horita","year":"1997","unstructured":"Horita, T., Takanami, I.: An efficiently reconfigurable architecture for mesh-arrays with PE and link faults. IEICE Trans. Inf. & Syst.\u00a0E80-D(9), 879\u2013885 (1997)","journal-title":"IEICE Trans. Inf. & Syst."}],"container-title":["Lecture Notes in Computer Science","Transactions on Computational Science XIII"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-22619-9_6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,13]],"date-time":"2019-06-13T18:10:34Z","timestamp":1560449434000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-22619-9_6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642226182","9783642226199"],"references-count":23,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-22619-9_6","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}