{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T00:00:00Z","timestamp":1740096000474,"version":"3.37.3"},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642231773"},{"type":"electronic","value":"9783642231780"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-23178-0_8","type":"book-chapter","created":{"date-parts":[[2011,9,10]],"date-time":"2011-09-10T03:15:58Z","timestamp":1315624558000},"page":"88-97","source":"Crossref","is-referenced-by-count":0,"title":["Cache Efficiency and Scalability on Multi-core Architectures"],"prefix":"10.1007","author":[{"given":"Thomas","family":"M\u00fcller","sequence":"first","affiliation":[]},{"given":"Carsten","family":"Trinitis","sequence":"additional","affiliation":[]},{"given":"Jasmin","family":"Smajic","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"8_CR1","unstructured":"OpenMP: The OpenMP API specification for parallel programming, \n                    \n                      http:\/\/www.openmp.org"},{"key":"8_CR2","unstructured":"Perf Wiki, \n                    \n                      https:\/\/perf.wiki.kernel.org"},{"key":"8_CR3","unstructured":"SuiteSparse: a Suite of Sparse matrix packages, \n                    \n                      http:\/\/www.cise.ufl.edu\/research\/sparse\/SuiteSparse\/"},{"key":"8_CR4","unstructured":"SuiteSparseQR: multithreaded multifrontal sparse QR factorization, \n                    \n                      http:\/\/www.cise.ufl.edu\/research\/sparse\/SPQR\/"},{"key":"8_CR5","unstructured":"AMD: AMD Core Math Library, \n                    \n                      http:\/\/www.amd.com\/acml\/"},{"key":"8_CR6","unstructured":"Amdahl, G.: Validity of the single processor approach to achieving large-scale computing capabilities. In: AFIPS Conference Proceedings, vol.\u00a030, pp. 483\u2013485 (1967), \n                    \n                      http:\/\/www-inst.eecs.berkeley.edu\/~n252\/paper\/Amdahl.pdf"},{"key":"8_CR7","unstructured":"Amestoy, P.R., Duff, I.S., Puglisi, C.: Multifrontal qr factorization in a multiprocessor environment. Numerical Linear Algebra with Applications 3(4), 275\u2013300 (1996), \n                    \n                      http:\/\/dx.doi.org\/10.1002\/SICI1099-150199607\/083:4275::AID-NLA833.0.CO2-7"},{"key":"8_CR8","unstructured":"Intel: Intel 64 and IA-32 Architectures Software Developers Manual; Volume 3B: System Programming Guide, Part 2, \n                    \n                      http:\/\/www.intel.com\/Assets\/PDF\/manual\/253669.pdf"},{"key":"8_CR9","unstructured":"Intel: Math Kernel Library, \n                    \n                      http:\/\/software.intel.com\/en-us\/articles\/intel-mkl\/"},{"key":"8_CR10","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"219","DOI":"10.1007\/978-3-642-19448-1_12","volume-title":"Transactions on High-Performance Embedded Architectures and Compilers III","author":"T. Klug","year":"2011","unstructured":"Klug, T., Ott, M., Weidendorfer, J., Trinitis, C.: autopin automated optimization of thread-to-core pinning on multicore systems. In: Stenstr\u00f6m, P. (ed.) Transactions on High-Performance Embedded Architectures and Compilers III. LNCS, vol.\u00a06590, pp. 219\u2013235. Springer, Heidelberg (2011), \n                    \n                      http:\/\/dx.doi.org\/10.1007\/978-3-642-19448-1_12"},{"issue":"1","key":"8_CR11","doi-asserted-by":"publisher","first-page":"82","DOI":"10.1137\/1034004","volume":"34","author":"J.W.H. Liu","year":"1992","unstructured":"Liu, J.W.H.: The multifrontal method for sparse matrix solution: Theory and practice. SIAM Review\u00a034(1), 82\u2013109 (1992), \n                    \n                      http:\/\/link.aip.org\/link\/?SIR\/34\/82\/1","journal-title":"SIAM Review"},{"key":"8_CR12","doi-asserted-by":"publisher","first-page":"89","DOI":"10.1023\/A:1008680131271","volume":"7","author":"P. Matstoms","year":"1997","unstructured":"Matstoms, P.: Sparse linear least squares problems in optimization. Computational Optimization and Applications\u00a07, 89\u2013110 (1997), \n                    \n                      http:\/\/dx.doi.org\/10.1023\/A:1008680131271","journal-title":"Computational Optimization and Applications"},{"issue":"2","key":"8_CR13","doi-asserted-by":"publisher","first-page":"295","DOI":"10.1109\/TPAS.1985.319043","volume":"104","author":"W. Tinney","year":"1985","unstructured":"Tinney, W., Brandwajn, V., Chan, S.: Sparse vector methods. IEEE Transactions on Power Apparatus and Systems PAS\u00a0104(2), 295\u2013301 (1985)","journal-title":"IEEE Transactions on Power Apparatus and Systems PAS"},{"key":"8_CR14","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"41","DOI":"10.1007\/978-3-642-03275-2_5","volume-title":"Parallel Computing Technologies","author":"C. Trinitis","year":"2009","unstructured":"Trinitis, C., K\u00fcstner, T., Weidendorfer, J., Smajic, J.: Sparse matrix operations on multi-core architectures. In: Malyshkin, V. (ed.) PaCT 2009. LNCS, vol.\u00a05698, pp. 41\u201348. Springer, Heidelberg (2009), \n                    \n                      http:\/\/dx.doi.org\/10.1007\/978-3-642-03275-2_5"},{"key":"8_CR15","doi-asserted-by":"crossref","unstructured":"Trinitis, C., K\u00fcstner, T., Weidendorfer, J., Smajic, J.: Sparse matrix operations on several multi-core architectures. The Journal of Supercomputing, 1\u20139 (2010), \n                    \n                      http:\/\/dx.doi.org\/10.1007\/s11227-010-0428-9","DOI":"10.1007\/s11227-010-0428-9"}],"container-title":["Lecture Notes in Computer Science","Parallel Computing Technologies"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-23178-0_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,3]],"date-time":"2019-04-03T02:39:23Z","timestamp":1554259163000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-23178-0_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642231773","9783642231780"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-23178-0_8","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}