{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,8]],"date-time":"2025-03-08T21:40:13Z","timestamp":1741470013978,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":31,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642233999"},{"type":"electronic","value":"9783642234002"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-23400-2_26","type":"book-chapter","created":{"date-parts":[[2011,8,17]],"date-time":"2011-08-17T11:34:15Z","timestamp":1313580855000},"page":"269-281","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Filtering Directory Lookups in CMPs with Write-Through Caches"],"prefix":"10.1007","author":[{"given":"Ana","family":"Bosque","sequence":"first","affiliation":[]},{"given":"Victor","family":"Vi\u00f1als","sequence":"additional","affiliation":[]},{"given":"Pablo","family":"Iba\u00f1ez","sequence":"additional","affiliation":[]},{"given":"Jose Maria","family":"Llaberia","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"26_CR1","doi-asserted-by":"crossref","unstructured":"Agarwal, A., Simoni, R., Hennessy, J., Horowitz, M.: An Evaluation of Directory Schemes for Cache Coherence. In: ISCA-15, pp. 280\u2013289 (1988)","DOI":"10.1145\/633625.52432"},{"key":"26_CR2","doi-asserted-by":"crossref","unstructured":"Agarwal, N., Peh, L.-S., Jha, N.: In-Network Coherence Filtering: Snoopy coherence without broadcasts, pp. 232\u2013243 (2009)","DOI":"10.1145\/1669112.1669143"},{"key":"26_CR3","doi-asserted-by":"crossref","unstructured":"Alameldeen, A.R., Wood, D.A.: Variability in Architectural Simulations of Multi-Threaded Workloads. In: HPCA-9, p. 7 (2003)","DOI":"10.1109\/HPCA.2003.1183520"},{"key":"26_CR4","unstructured":"AMD. AMD Multi-Core Technology, http:\/\/multicore.amd.com"},{"key":"26_CR5","doi-asserted-by":"crossref","unstructured":"Ballapuram, C.S., Sharif, A., Lee, H.-H.S.: Exploiting Access Semantics and Program Behavior to Reduce Snoop Power in Chip Multiprocessors. In: ASPLOS XIII, pp. 60\u201369 (2008)","DOI":"10.1145\/1353535.1346290"},{"key":"26_CR6","doi-asserted-by":"crossref","unstructured":"Barroso, L.A., et al.: Piranha: a Scalable Architecture Based on Single-Chip Multiprocessing. In: ISCA-27, pp. 282\u2013293 (2000)","DOI":"10.1145\/342001.339696"},{"key":"26_CR7","doi-asserted-by":"crossref","unstructured":"Cantin, J.F., Lipasti, M.H., Smith, J.E.: Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking. In: ISCA-32, pp. 246\u2013257 (June 2005)","DOI":"10.1145\/1080695.1069991"},{"issue":"12","key":"26_CR8","doi-asserted-by":"publisher","first-page":"1112","DOI":"10.1109\/TC.1978.1675013","volume":"C-27","author":"L.M. Censier","year":"1978","unstructured":"Censier, L.M., Feautrier, P.: A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers\u00a0C-27(12), 1112\u20131118 (1978)","journal-title":"IEEE Transactions on Computers"},{"key":"26_CR9","doi-asserted-by":"crossref","unstructured":"Charlesworth, A., Aneshansley, N., Haakmeester, M., Drogichen, D., Gilbert, G., Williams, R., Phelps, A.: The Starfire SMP Interconnect, p. 37 (1997)","DOI":"10.1145\/509593.509630"},{"key":"26_CR10","doi-asserted-by":"crossref","unstructured":"Dash, A., Petrov, P.: Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering. In: DSD 2006, pp. 79\u201382 (2006)","DOI":"10.1109\/DSD.2006.50"},{"key":"26_CR11","unstructured":"Ekman, M., Dahlgren, F., Stenstr\u00f6m, P.: Evaluation of Snoop-Energy Reduction Techniques for Chip-Multiprocessors. In: Workshop on Duplicating, Deconstructing and Debunking, in conjunction with ISCA (May 2002)"},{"key":"26_CR12","doi-asserted-by":"crossref","unstructured":"Ekman, M., Stenstr\u00f6m, P., Dahlgren, F.: TLB and Snoop Energy-Reduction Using Virtual Caches in Low-Power Chip-Multiprocessors. In: ISLPED 2002, pp. 243\u2013246 (2002)","DOI":"10.1145\/566408.566471"},{"key":"26_CR13","unstructured":"Fujitsu. Fujitsu SPARC64 VII Processor (June 2008)"},{"key":"26_CR14","unstructured":"Gupta, A., dietrich Weber, W., Mowry, T.: Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes. In: ICPP 1990, pp. 312\u2013321 (1990)"},{"key":"26_CR15","unstructured":"http:\/\/www.spec.org\/web2005\/"},{"key":"26_CR16","unstructured":"Intel. Leading Virtualization Performance and Energy Efficiency in a Multi-processor Server"},{"key":"26_CR17","doi-asserted-by":"crossref","unstructured":"Jerger, N.: SigNet: Network-on-chip filtering for coarse vector directories. pp. 1378\u20131383 (2010)","DOI":"10.1109\/DATE.2010.5457028"},{"key":"26_CR18","doi-asserted-by":"crossref","unstructured":"Johnson, T., Nawathe, U.: An 8-core, 64-thread, 64-bit Power Efficient SPARC SOC (niagara2). In: ISPD 2007, p. 2 (2007)","DOI":"10.1145\/1231996.1232000"},{"key":"26_CR19","doi-asserted-by":"crossref","unstructured":"Laudon, J., Lenoski, D.: The SGI Origin: A ccnuma Highly Scalable Server, pp. 241\u2013251 (1997)","DOI":"10.1145\/384286.264206"},{"issue":"6","key":"26_CR20","doi-asserted-by":"publisher","first-page":"639","DOI":"10.1147\/rd.516.0639","volume":"51","author":"H.Q. Le","year":"2007","unstructured":"Le, H.Q., et al.: IBM POWER6 microarchitecture. IBM J. Res. Dev.\u00a051(6), 639\u2013662 (2007)","journal-title":"IBM J. Res. Dev."},{"issue":"2","key":"26_CR21","doi-asserted-by":"publisher","first-page":"50","DOI":"10.1109\/2.982916","volume":"35","author":"P. Magnusson","year":"2002","unstructured":"Magnusson, P., Christensson, M., Eskilson, J., Forsgren, D., Hallberg, G., Hogberg, J., Larsson, F., Moestedt, A., Werner, B.: Simics: A Full System Simulation Platform. Computer\u00a035(2), 50\u201358 (2002)","journal-title":"Computer"},{"issue":"2","key":"26_CR22","doi-asserted-by":"publisher","first-page":"10","DOI":"10.1145\/1577129.1577133","volume":"37","author":"M. Monchiero","year":"2009","unstructured":"Monchiero, M., Ahn, J.H., Falc\u00f3n, A., Ortega, D., Faraboschi, P.: How to Simulate 1000 Cores. SIGARCH Comput. Archit. News\u00a037(2), 10\u201319 (2009)","journal-title":"SIGARCH Comput. Archit. News"},{"key":"26_CR23","doi-asserted-by":"crossref","unstructured":"Moshovos, A.: RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence. In: ISCA-32, pp. 234\u2013245 (June 2005)","DOI":"10.1145\/1080695.1069990"},{"key":"26_CR24","unstructured":"Moshovos, A., Memik, G., Falsafi, B., Choudhary, A.: JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers. In: HPCA-7, 2001, pp. 85\u201396 (2001)"},{"key":"26_CR25","unstructured":"Muralimanohar, N., Balasubramonian, R.: CACTI 6.0: A Tool to Model Large Caches (2009)"},{"key":"26_CR26","doi-asserted-by":"crossref","unstructured":"Salapura, V., Blumrich, M., Gara, A.: Improving the Accuracy of Snoop Filtering Using Stream Registers. In: MEDEA 2007, pp. 25\u201332 (2007)","DOI":"10.1145\/1327171.1327174"},{"key":"26_CR27","doi-asserted-by":"crossref","unstructured":"Singh, J.P., Gupta, A., Ohara, M., Torrie, E., Woo, S.C.: The SPLASH-2 Programs: Characterization and Methodological Considerations. In: ISCA-22, p. 24 (1995)","DOI":"10.1145\/225830.223990"},{"key":"26_CR28","unstructured":"Steinman, M.B., Harris, G.J., Kocev, A., Lamere, V.C., Pannell, R.D.: The AlphaServer 4100 Cached Processor Module Architecture and Design (1996)"},{"issue":"2","key":"26_CR29","doi-asserted-by":"publisher","first-page":"327","DOI":"10.1145\/1150019.1136514","volume":"34","author":"K. Strauss","year":"2006","unstructured":"Strauss, K., Shen, X., Torrellas, J.: Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors. SIGARCH Comput. Archit. News\u00a034(2), 327\u2013338 (2006)","journal-title":"SIGARCH Comput. Archit. News"},{"key":"26_CR30","unstructured":"Sun Microsystems, Inc. OpenSPARC T2 System-On-Chip (SoC) Microarchitecture Specification vol. 1 (May 2008)"},{"key":"26_CR31","doi-asserted-by":"crossref","unstructured":"Tang, C.K.: Cache System Design in the Tightly Coupled Multiprocessor System. In: AFIPS 1976, pp. 749\u2013753 (1976)","DOI":"10.1145\/1499799.1499901"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2011 Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-23400-2_26","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,8]],"date-time":"2025-03-08T21:00:19Z","timestamp":1741467619000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-23400-2_26"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642233999","9783642234002"],"references-count":31,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-23400-2_26","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]},"assertion":[{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}