{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,8]],"date-time":"2025-03-08T21:40:09Z","timestamp":1741470009252,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642233999"},{"type":"electronic","value":"9783642234002"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-23400-2_27","type":"book-chapter","created":{"date-parts":[[2011,8,17]],"date-time":"2011-08-17T11:34:15Z","timestamp":1313580855000},"page":"282-294","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["FELI: HW\/SW Support for On-Chip Distributed Shared Memory in Multicores"],"prefix":"10.1007","author":[{"given":"Carlos","family":"Villavieja","sequence":"first","affiliation":[]},{"given":"Yoav","family":"Etsion","sequence":"additional","affiliation":[]},{"given":"Alex","family":"Ramirez","sequence":"additional","affiliation":[]},{"given":"Nacho","family":"Navarro","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"issue":"1","key":"27_CR1","doi-asserted-by":"publisher","first-page":"6","DOI":"10.1145\/581888.581891","volume":"1","author":"O. Avissar","year":"2002","unstructured":"Avissar, O., Barua, R., Stewart, D.: An optimal memory allocation scheme for scratch-pad-based embedded systems. ACM Trans. Embed. Comput. Syst.\u00a01(1), 6\u201326 (2002)","journal-title":"ACM Trans. Embed. Comput. Syst."},{"key":"27_CR2","doi-asserted-by":"crossref","unstructured":"Banakar, R., Steinke, S., Lee, B.S., Balakrishnan, M., Marwedel, P.: Scratchpad memory: design alternative for cache on-chip memory in embedded systems. In: CODES 2002: Proceedings of the Tenth International Symposium on Hardware\/Software Codesign, pp. 73\u201378 (2002)","DOI":"10.1145\/774789.774805"},{"key":"27_CR3","doi-asserted-by":"crossref","unstructured":"Bienia, C., Kumar, S., Singh, J.P., Li, K.: The PARSEC benchmark suite: Characterization and architectural implications (October 2008)","DOI":"10.1145\/1454115.1454128"},{"key":"27_CR4","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"3","DOI":"10.1007\/978-3-540-74466-5_2","volume-title":"Euro-Par 2007 Parallel Processing","author":"M. Casas","year":"2007","unstructured":"Casas, M., Badia, R.M., Labarta, J.: Automatic structure extraction from MPI applications tracefiles. In: Kermarrec, A.-M., Boug\u00e9, L., Priol, T. (eds.) Euro-Par 2007. LNCS, vol.\u00a04641, pp. 3\u201312. Springer, Heidelberg (2007)"},{"key":"27_CR5","doi-asserted-by":"publisher","first-page":"13","DOI":"10.1109\/TVLSI.2006.887813","volume":"15","author":"Y.-J. Chang","year":"2007","unstructured":"Chang, Y.-J., Lan, M.-F.: Two new techniques integrated for energy-efficient tlb design. IEEE Trans. Very Large Scale Integr. Syst.\u00a015, 13\u201323 (2007)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"27_CR6","doi-asserted-by":"crossref","unstructured":"Chaudhuri, M.: Pagenuca: Selected policies for page-grain locality management in large shared chipmultiprocessor caches. In: In Proceedings of HPCA-15 (2009)","DOI":"10.1109\/HPCA.2009.4798258"},{"key":"27_CR7","doi-asserted-by":"crossref","unstructured":"Corbalan, J., Martorell, X., Labarta, J.: Evaluation of the memory page migration influence in the system performance: the case of the SGI o2000. In: ICS 2003: Proceedings of the 17th annual international conference on Supercomputing, pp. 121\u2013129 (2003)","DOI":"10.1145\/782814.782833"},{"key":"27_CR8","doi-asserted-by":"crossref","unstructured":"Etsion, Y., Feitelson, D.G.: L1 cache filtering through random selection of memory references. In: PACT, pp. 235\u2013244 (2007)","DOI":"10.1109\/PACT.2007.4336215"},{"key":"27_CR9","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1145\/1054907.1054913","volume":"31","author":"G. Hamerly","year":"2004","unstructured":"Hamerly, G., Perelman, E., Calder, B.: How to use simpoint to pick simulation points. SIGMETRICS Perform. Eval. Rev.\u00a031, 25\u201330 (2004)","journal-title":"SIGMETRICS Perform. Eval. Rev."},{"issue":"2","key":"27_CR10","doi-asserted-by":"publisher","first-page":"104","DOI":"10.1145\/68182.68192","volume":"17","author":"M.A. Holliday","year":"1989","unstructured":"Holliday, M.A.: Reference history, page size, and migration daemons in local\/remote architectures. SIGARCH Comput. Archit. News\u00a017(2), 104\u2013112 (1989)","journal-title":"SIGARCH Comput. Archit. News"},{"key":"27_CR11","doi-asserted-by":"crossref","unstructured":"Luk, C.K., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Reddi, V.J., Hazelwood, K.: Pin: building customized program analysis tools with dynamic instrumentation, pp. 190\u2013200 (2005)","DOI":"10.1145\/1064978.1065034"},{"issue":"1","key":"27_CR12","doi-asserted-by":"publisher","first-page":"69","DOI":"10.1109\/MM.2008.2","volume":"28","author":"N. Muralimanohar","year":"2008","unstructured":"Muralimanohar, N., Balasubramonian, R., Jouppi, N.P.: Architecting efficient interconnects for large caches with cacti 6.0. IEEE Micro\u00a028(1), 69\u201379 (2008)","journal-title":"IEEE Micro"},{"issue":"3","key":"27_CR13","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1509288.1509293","volume":"8","author":"N. Nguyen","year":"2009","unstructured":"Nguyen, N., Dominguez, A., Barua, R.: Memory allocation for embedded systems with a compile-time-unknown scratch-pad size. ACM Trans. Embed. Comput. Syst.\u00a08(3), 1\u201332 (2009)","journal-title":"ACM Trans. Embed. Comput. Syst."},{"key":"27_CR14","doi-asserted-by":"crossref","unstructured":"Nikolopoulos, D.S., Papatheodorou, T.S., Polychronopoulos, C.D., Labarta, J., Ayguad\u00e9, E.: User-level dynamic page migration for multiprogrammed shared-memory multiprocessors. In: ICPP 2000: Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing, p. 95 (2000)","DOI":"10.1109\/ICPP.2000.876083"},{"key":"27_CR15","unstructured":"Rico, A., Cabarcas, F., Quesada, A., Pavlovic, M., Vega, A.J., Villavieja, C., Etsion, Y., Ramirez, A.: Scalable simulation of decoupled accelerator architectures. Tech. Rep. UPC-DAC-RR-2010-14, Universitat Polit\u00e8cnica de Catalunya (June 2010)"},{"key":"27_CR16","doi-asserted-by":"publisher","first-page":"1154","DOI":"10.1109\/12.30869","volume":"38","author":"C. Scheurich","year":"1989","unstructured":"Scheurich, C., Dubois, M.: Dynamic page migration in multiprocessors with distributed global memory. IEEE Transactions on Computers\u00a038, 1154\u20131163 (1989)","journal-title":"IEEE Transactions on Computers"},{"key":"27_CR17","doi-asserted-by":"crossref","unstructured":"Swaminathan, S., Patel, S.B., Dieffenderfer, J., Silberman, J.: Reducing power consumption during tlb lookups in a powerpc\u201d embedded processor. In: Proceedings of the 6th International Symposium on Quality of Electronic Design, ISQED 2005, pp. 54\u201358 (2005)","DOI":"10.1109\/ISQED.2005.103"},{"issue":"2","key":"27_CR18","doi-asserted-by":"publisher","first-page":"472","DOI":"10.1145\/1151074.1151085","volume":"5","author":"S. Udayakumaran","year":"2006","unstructured":"Udayakumaran, S., Dominguez, A., Barua, R.: Dynamic allocation for scratch-pad memory using compile-time decisions. ACM Trans. Embed. Comput. Syst.\u00a05(2), 472\u2013511 (2006)","journal-title":"ACM Trans. Embed. Comput. Syst."},{"key":"27_CR19","unstructured":"Villavieja, C., Ramirez, A., Navarro, N.: On-chip distributed shared memory. Tech. Rep. UPC-DAC-RR-CAP-2011, Universitat Polit\u00e8cnica de Catalunya (February 2011)"},{"key":"27_CR20","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"242","DOI":"10.1007\/978-3-540-68555-5_20","volume-title":"OpenMP Shared Memory Parallel Programming","author":"W.-C. Jeun","year":"2008","unstructured":"Jeun, W.-C., Kee, Y.-S., Ha, S.: Improving performance of openMP for SMP clusters through overlapped page migrations. In: Mueller, M.S., Chapman, B.M., de Supinski, B.R., Malony, A.D., Voss, M. (eds.) IWOMP 2005 and IWOMP 2006. LNCS, vol.\u00a04315, pp. 242\u2013252. Springer, Heidelberg (2008)"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2011 Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-23400-2_27","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,8]],"date-time":"2025-03-08T21:00:44Z","timestamp":1741467644000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-23400-2_27"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642233999","9783642234002"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-23400-2_27","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]},"assertion":[{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}