{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,12]],"date-time":"2025-03-12T04:44:27Z","timestamp":1741754667019,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":39,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642239502"},{"type":"electronic","value":"9783642239519"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-23951-9_1","type":"book-chapter","created":{"date-parts":[[2011,9,26]],"date-time":"2011-09-26T05:17:11Z","timestamp":1317014231000},"page":"1-16","source":"Crossref","is-referenced-by-count":1,"title":["An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension"],"prefix":"10.1007","author":[{"given":"Philipp","family":"Grabher","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Johann","family":"Gro\u00dfsch\u00e4dl","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Simon","family":"Hoerder","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kimmo","family":"J\u00e4rvinen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dan","family":"Page","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefan","family":"Tillich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marcin","family":"W\u00f3jcik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"12","key":"1_CR1","doi-asserted-by":"publisher","first-page":"3179","DOI":"10.1093\/ietcom\/e89-b.12.3179","volume":"E89-B","author":"H. Amano","year":"2006","unstructured":"Amano, H.: A survey on dynamically reconfigurable processors. IEICE Tran. Comm.\u00a0E89-B(12), 3179\u20133187 (2006)","journal-title":"IEICE Tran. Comm."},{"key":"1_CR2","doi-asserted-by":"crossref","unstructured":"Banakar, R., Steinke, S., Lee, B.-S., Balakrishnan, M., Marwedel, P.: Scratchpad memory: design alternative for cache on-chip memory in embedded systems. In: CODES, pp. 73\u201378 (2002)","DOI":"10.1145\/774789.774805"},{"issue":"2","key":"1_CR3","doi-asserted-by":"publisher","first-page":"247","DOI":"10.1007\/s00145-010-9083-9","volume":"24","author":"G. Canivet","year":"2011","unstructured":"Canivet, G., Maistri, P., Leveugle, R., Cl\u00e9di\u00e8re, J., Valette, F., Renaudin, M.: Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA. J. Cryptology\u00a024(2), 247\u2013268 (2011)","journal-title":"J. Cryptology"},{"issue":"3","key":"1_CR4","doi-asserted-by":"publisher","first-page":"26","DOI":"10.1109\/40.502403","volume":"16","author":"\u00c7.K. Ko\u00e7","year":"1996","unstructured":"Ko\u00e7, \u00c7.K., Acar, T., Kaliski, B.S.: Analyzing and comparing Montgomery multiplication algorithms. IEEE Micro\u00a016(3), 26\u201333 (1996)","journal-title":"IEEE Micro"},{"key":"1_CR5","unstructured":"Chan, H., Schaumont, P., Verbauwhede, I.: Process isolation for reconfigurable hardware. In: ERSA, pp. 164\u2013170 (2006)"},{"key":"1_CR6","unstructured":"Dales, M.W.: Managing a reconfigurable processor in a general purpose workstation environment. PhD thesis, University of Glasgow (2003)"},{"key":"1_CR7","series-title":"Lecture Notes in Computer Science","first-page":"111","volume-title":"Advances in Cryptology - CRYPTO \u201986","author":"Y.G. Desmedt","year":"1987","unstructured":"Desmedt, Y.G., Quisquater, J.-J.: Public-key systems based on the difficulty of tampering. In: Odlyzko, A.M. (ed.) CRYPTO 1986. LNCS, vol.\u00a0263, pp. 111\u2013117. Springer, Heidelberg (1987)"},{"key":"1_CR8","doi-asserted-by":"crossref","unstructured":"Flynn, M.J., McLaren, M.D.: Microprogramming revisited. In: Proc. of the 22nd ACM National Conference, pp. 457\u2013464 (1967)","DOI":"10.1145\/800196.806013"},{"issue":"2","key":"1_CR9","doi-asserted-by":"publisher","first-page":"87","DOI":"10.1049\/ip-cdt:20050131","volume":"153","author":"I. Gonzalez","year":"2006","unstructured":"Gonzalez, I., G\u00f3mez-Arribas, F.: Ciphering algorithms in MicroBlaze-based embedded systems. Computers and Digital Techniques\u00a0153(2), 87\u201392 (2006)","journal-title":"Computers and Digital Techniques"},{"key":"1_CR10","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"331","DOI":"10.1007\/978-3-540-85053-3_21","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2008","author":"P. Grabher","year":"2008","unstructured":"Grabher, P., Gro\u00dfsch\u00e4dl, J., Page, D.: Light-weight instruction set extensions for bit-sliced cryptography. In: Oswald, E., Rohatgi, P. (eds.) CHES 2008. LNCS, vol.\u00a05154, pp. 331\u2013345. Springer, Heidelberg (2008)"},{"key":"1_CR11","doi-asserted-by":"crossref","unstructured":"Gro\u00dfsch\u00e4dl, J., Tillich, S., Szekely, A.: Performance evaluation of instruction set extensions for long integer modular arithmetic on a SPARC V8 processor. In: DSD, pp. 680\u2013689 (2007)","DOI":"10.1109\/DSD.2007.4341542"},{"key":"1_CR12","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"291","DOI":"10.1007\/978-3-540-48302-1_30","volume-title":"Field Programmable Logic and Applications","author":"I. Had\u017ei\u0107","year":"1999","unstructured":"Had\u017ei\u0107, I., Udani, S., Smith, J.M.: FPGA viruses. In: Lysaght, P., Irvine, J., Hartenstein, R.W. (eds.) FPL 1999. LNCS, vol.\u00a01673, pp. 291\u2013300. Springer, Heidelberg (1999)"},{"key":"1_CR13","doi-asserted-by":"crossref","unstructured":"Hines, S.R., Green, J., Tyson, G., Whalley, D.: Improving program efficiency by packing instructions into registers. In: ISCA, pp. 260\u2013271 (2005)","DOI":"10.1109\/ISCA.2005.32"},{"key":"1_CR14","doi-asserted-by":"crossref","unstructured":"Hodjat, A., Verbauwhede, I.: Interfacing a high speed crypto accelerator to an embedded CPU. In: Asilomar Conference on Signals, Systems, and Computers, vol.\u00a01, pp. 488\u2013492 (2004)","DOI":"10.1109\/ACSSC.2004.1399180"},{"key":"1_CR15","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"160","DOI":"10.1007\/978-3-642-21040-2_11","volume-title":"WISTP","author":"S. Hoerder","year":"2011","unstructured":"Hoerder, S., W\u00f3jcik, M., Tillich, S., Page, D.: An evaluation of hash functions on a power analysis resistant processor architecture. In: Ardagna, C. (ed.) WISTP 2011. LNCS, vol.\u00a06633, pp. 160\u2013174. Springer, Heidelberg (2011)"},{"key":"1_CR16","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9157-4","volume-title":"Handbook of FPGA Design Security","author":"T. Huffmire","year":"2010","unstructured":"Huffmire, T., Irvine, C., Nguyen, T.D., Levin, T., Kastner, R., Sherwood, T.: Handbook of FPGA Design Security. Springer, Heidelberg (2010)"},{"key":"1_CR17","doi-asserted-by":"crossref","unstructured":"Juliato, M., Gebotys, C.: Tailoring a reconfigurable platform to SHA-256 and HMAC through custom instructions and peripherals. In: ReConFig, pp. 195\u2013200 (2009)","DOI":"10.1109\/ReConFig.2009.40"},{"key":"1_CR18","doi-asserted-by":"crossref","unstructured":"Kastner, R., Levin, T., Nguyen, T., Irvine, C., Brotherton, B., Wang, G., Sherwood, T., Huffmire, T.: Moats and drawbridges: An isolation primitive for reconfigurable hardware based systems. In: IEEE Security and Privacy, pp. 281\u2013295 (2007)","DOI":"10.1109\/SP.2007.28"},{"key":"1_CR19","doi-asserted-by":"crossref","unstructured":"Kluter, T., Brisk, P., Ienne, P., Charbon, E.: Way stealing: cache-assisted automatic instruction set extensions. In: DAC, pp. 31\u201336 (2009)","DOI":"10.1145\/1629911.1629923"},{"key":"1_CR20","doi-asserted-by":"crossref","unstructured":"Kocher, P.C., Lee, R.B., McGraw, G., Raghunathan, A.: Security as a new dimension in embedded system design. In: DAC, pp. 753\u2013760 (2004)","DOI":"10.1145\/996566.996771"},{"issue":"3","key":"1_CR21","doi-asserted-by":"publisher","first-page":"659","DOI":"10.1145\/1142980.1142986","volume":"11","author":"R. Lysecky","year":"2006","unstructured":"Lysecky, R., Stitt, G., Vahid, F.: Warp processors. TODAES\u00a011(3), 659\u2013681 (2006)","journal-title":"TODAES"},{"issue":"1-2","key":"1_CR22","doi-asserted-by":"publisher","first-page":"149","DOI":"10.1145\/144965.145794","volume":"23","author":"N. Malik","year":"1992","unstructured":"Malik, N., Eickemeyer, R.J., Vassiliadis, S.: Interlock collapsing ALU for increased instruction-level parallelism. SIGMICRO Newsletter\u00a023(1-2), 149\u2013157 (1992)","journal-title":"SIGMICRO Newsletter"},{"key":"1_CR23","doi-asserted-by":"crossref","unstructured":"Miller, J.E., Agarwal, A.: Software-based instruction caching for embedded processors. In: ASPLOS, pp. 293\u2013302 (2006)","DOI":"10.1145\/1168857.1168894"},{"key":"1_CR24","doi-asserted-by":"crossref","unstructured":"Moore, C.R., Balser, D.M., Muhich, J.S., East, R.E.: IBM single chip RISC processor (RSC). In: ICCD, pp. 200\u2013204 (1991)","DOI":"10.1109\/ICCD.1992.276248"},{"key":"1_CR25","doi-asserted-by":"crossref","unstructured":"Pothineni, N., Brisk, P., Ienne, P., Kumar, A., Paul, K.: A high-level synthesis flow for custom instruction set extensions for application-specific processors. In: ASP-DAC, pp. 707\u2013712 (2010)","DOI":"10.1109\/ASPDAC.2010.5419795"},{"issue":"3","key":"1_CR26","doi-asserted-by":"publisher","first-page":"461","DOI":"10.1145\/1015047.1015049","volume":"3","author":"S. Ravi","year":"2004","unstructured":"Ravi, S., Raghunathan, A., Kocher, P.C., Hattangady, S.: Security in embedded systems: Design challenges. TECS\u00a03(3), 461\u2013491 (2004)","journal-title":"TECS"},{"key":"1_CR27","doi-asserted-by":"crossref","unstructured":"Schaumont, P., Sakiyama, K., Hodjat, A., Verbauwhede, I.: Embedded software integration for coarse-grain reconfigurable systems. In: IPDPS, pp. 137\u2013142 (2004)","DOI":"10.1109\/IPDPS.2004.1303110"},{"key":"1_CR28","unstructured":"Segars, S.: Low power design techniques for microprocessors (tutorial session). In: ISSCC (2001)"},{"key":"1_CR29","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"231","DOI":"10.1007\/3-540-48059-5_20","volume-title":"Cryptographic Hardware and Embedded Systems","author":"R.R. Taylor","year":"1999","unstructured":"Taylor, R.R., Goldstein, S.C.: A high-performance flexible architecture for cryptography. In: Ko\u00e7, \u00c7.K., Paar, C. (eds.) CHES 1999. LNCS, vol.\u00a01717, pp. 231\u2013245. Springer, Heidelberg (1999)"},{"key":"1_CR30","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"282","DOI":"10.1007\/978-3-540-30102-8_24","volume-title":"Advances in Computer Systems Architecture","author":"S. Tillich","year":"2004","unstructured":"Tillich, S., Gro\u00dfsch\u00e4dl, J.: A simple architectural enhancement for fast and flexible elliptic curve cryptography over binary finite fields GF(2 m ). In: Yew, P.-C., Xue, J. (eds.) ACSAC 2004. LNCS, vol.\u00a03189, pp. 282\u2013295. Springer, Heidelberg (2004)"},{"key":"1_CR31","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"270","DOI":"10.1007\/11894063_22","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2006","author":"S. Tillich","year":"2006","unstructured":"Tillich, S., Gro\u00dfsch\u00e4dl, J.: Instruction set extensions for efficient AES implementation on 32-bit processors. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol.\u00a04249, pp. 270\u2013284. Springer, Heidelberg (2006)"},{"issue":"4","key":"1_CR32","doi-asserted-by":"crossref","first-page":"240","DOI":"10.1145\/362575.362580","volume":"14","author":"A.B. Tucker","year":"1971","unstructured":"Tucker, A.B., Flynn, M.J.: Dynamic microprogramming: processor organization and programming. CACM\u00a014(4), 240\u2013250 (1971)","journal-title":"CACM"},{"key":"1_CR33","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"208","DOI":"10.1007\/978-3-540-73489-5_11","volume-title":"Pairing-Based Cryptography \u2013 Pairing 2007","author":"T. Vejda","year":"2007","unstructured":"Vejda, T., Page, D., Gro\u00dfsch\u00e4dl, J.: Instruction set extensions for pairing-based cryptography. In: Takagi, T., Okamoto, T., Okamoto, E., Okamoto, T. (eds.) Pairing 2007. LNCS, vol.\u00a04575, pp. 208\u2013224. Springer, Heidelberg (2007)"},{"key":"1_CR34","unstructured":"VeriSign.: An evaluation of new processor instructions for accelerating selected cryptographic algorithms (2010)"},{"key":"1_CR35","doi-asserted-by":"crossref","unstructured":"Wang, Z., Lee, R.B.: Covert and side channels due to processor architecture. In: ACSAC, pp. 473\u2013482 (2006)","DOI":"10.1109\/ACSAC.2006.20"},{"key":"1_CR36","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"91","DOI":"10.1007\/978-3-540-45234-8_10","volume-title":"Field Programmable Logic and Application","author":"T. Wollinger","year":"2003","unstructured":"Wollinger, T., Paar, C.: How secure are FPGAs in cryptographic applications? In FPL. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol.\u00a02778, pp. 91\u2013100. Springer, Heidelberg (2003)"},{"key":"1_CR37","doi-asserted-by":"crossref","unstructured":"Wu, L., Weaver, C., Austin, T.: CryptoManiac: a fast flexible architecture for secure communication. In: ISCA, pp. 110\u2013119 (2001)","DOI":"10.1145\/379240.379256"},{"key":"1_CR38","unstructured":"Xilinx. Partial reconfiguration user guide (UG702) v12.1 (2010), http:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx12_1\/ug702.pdf"},{"key":"1_CR39","unstructured":"Yang, B., Wu, K., Karri, R.: Scan based side channel attack on dedicated hardware implementations of data encryption standard. In: ITC, pp. 339\u2013344 (2004)"}],"container-title":["Lecture Notes in Computer Science","Cryptographic Hardware and Embedded Systems \u2013 CHES 2011"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-23951-9_1.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,12]],"date-time":"2025-03-12T01:15:38Z","timestamp":1741742138000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-23951-9_1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642239502","9783642239519"],"references-count":39,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-23951-9_1","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}