{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T09:06:40Z","timestamp":1725613600790},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642241536"},{"type":"electronic","value":"9783642241543"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-24154-3_10","type":"book-chapter","created":{"date-parts":[[2011,9,23]],"date-time":"2011-09-23T23:38:58Z","timestamp":1316821138000},"page":"92-101","source":"Crossref","is-referenced-by-count":1,"title":["Performance-Driven Clustering of Asynchronous Circuits"],"prefix":"10.1007","author":[{"given":"Georgios D.","family":"Dimou","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peter A.","family":"Beerel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrew M.","family":"Lines","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"10_CR1","doi-asserted-by":"crossref","unstructured":"Beerel, P.A., Lines, A., Davies, M., Kim, N.H.: Slack matching asynchronous designs. In: IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), pp. 184\u2013194 (2006)","DOI":"10.1109\/ASYNC.2006.26"},{"key":"10_CR2","doi-asserted-by":"crossref","unstructured":"Beerel, P.A., Dimou, G.D., Lines, A.: Proteus: An ASIC flow for GHz Asynchronous Designs. IEEE Design & Test (September\/October 2011)","DOI":"10.1109\/MDT.2011.114"},{"key":"10_CR3","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511674730","volume-title":"A Designer\u2019s Guide to Asynchronous VLSI","author":"P.A. Beerel","year":"2010","unstructured":"Beerel, P.A., Ozdag, R.O., Ferretti, M.: A Designer\u2019s Guide to Asynchronous VLSI. Cambridge University Press, Cambridge (2010)"},{"key":"10_CR4","doi-asserted-by":"crossref","unstructured":"van Berkel, K., Kessels, J., Roncken, M., Saeijs, R., Schalij, F.: The VLSI-Programming Language Tangram and Its Translation into Handshake Circuits. In: Proc. European Conference on Design Automation (EDAC), pp. 384\u2013389 (1991)","DOI":"10.1109\/EDAC.1991.206431"},{"key":"10_CR5","doi-asserted-by":"crossref","unstructured":"Cortadella, J., Kondratyev, A., Lavagno, L., Sotiriou, C.: De-synchronization: Synthesis of Asynchronous Circuits from Synchronous Specification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (October 2006)","DOI":"10.1109\/TCAD.2005.860958"},{"key":"10_CR6","doi-asserted-by":"crossref","unstructured":"Venkataramani, G., Goldstein, S.C.: Operation Chaining Asynchronous Pipelined Circuits. In: Proceedings of the International Conference on Computer Aided Design (ICCAD) (November 2007)","DOI":"10.1109\/ICCAD.2007.4397305"},{"key":"10_CR7","unstructured":"Dimou, G.: Clustering and Fanout Optimizations of Asynchronous Circuits. PhD. Thesis. University of Southern California (May 2009)"},{"key":"10_CR8","doi-asserted-by":"crossref","unstructured":"Golani, P., Beerel, P.A.: An area-efficient multi-level single-track pipeline template. In: Design, Automation & Test in Europe Conference & Exhibition (DATE) (March 2011)","DOI":"10.1109\/DATE.2011.5763322"},{"issue":"4","key":"10_CR9","doi-asserted-by":"publisher","first-page":"107","DOI":"10.1109\/MDT.2002.1018139","volume":"19","author":"A. Kondratyev","year":"2002","unstructured":"Kondratyev, A., Lwin, K.: Design of asynchronous circuits by synchronous CAD tools. IEEE Design and Test of Computers\u00a019(4), 107\u2013117 (2002)","journal-title":"IEEE Design and Test of Computers"},{"key":"10_CR10","doi-asserted-by":"crossref","unstructured":"Reese, R.B., Thornton, M.A., Traver, C.: A fine-grain Phased Logic CPU. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI (February 2003)","DOI":"10.1109\/ISVLSI.2003.1183355"},{"key":"10_CR11","doi-asserted-by":"crossref","unstructured":"Reese, R.B., Thornton, M.A., Traver, C.: A coarse-grain phased logic CPU. IEEE Transactions on Computers (July 2005)","DOI":"10.1109\/TC.2005.105"},{"key":"10_CR12","doi-asserted-by":"crossref","unstructured":"Smirnov, B., Taubin, A., Su, M., Karpovsky, M.G.: An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library. In: Proc. of 5th International Conference on Application of Concurrency to System Design, ACSD (2005)","DOI":"10.1109\/ACSD.2005.3"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-24154-3_10","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,16]],"date-time":"2019-06-16T05:39:06Z","timestamp":1560663546000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-24154-3_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642241536","9783642241543"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-24154-3_10","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}