{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T09:06:46Z","timestamp":1725613606948},"publisher-location":"Berlin, Heidelberg","reference-count":19,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642241536"},{"type":"electronic","value":"9783642241543"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-24154-3_26","type":"book-chapter","created":{"date-parts":[[2011,9,23]],"date-time":"2011-09-23T23:38:58Z","timestamp":1316821138000},"page":"257-266","source":"Crossref","is-referenced-by-count":2,"title":["High-Speed and Low-Power PID Structures for Embedded Applications"],"prefix":"10.1007","author":[{"given":"Abdelkrim K.","family":"Oudjida","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nicolas","family":"Chaillet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ahmed","family":"Liacha","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mustapha","family":"Hamerlain","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohamed L.","family":"Berrandjia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"unstructured":"\u00c5str\u00f6m, K., H\u00e4gglund, T.: PID Controllers: Theory, Design, and Tuning, 2nd edn. The Instrument Society of America, Research Triangle Park, NC, USA (1995) ISBN: 1-55617-516-7, Copyright","key":"26_CR1"},{"unstructured":"Zhao, W., et al.: FPGA Implementation of Closed-Loop Control Systems for Small-Scale Robot. In: Proceedings of the IEEE 12th International on Advanced Robotics (ICAR), pp. 70\u201377 (2005)","key":"26_CR2"},{"doi-asserted-by":"crossref","unstructured":"Samet, L., et al.: A Digital PID Controller for Real-Time and Multi-Loop Control: a Comparative Study. In: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (ICECS), vol.\u00a01, pp. 291\u2013296 (1998)","key":"26_CR3","DOI":"10.1109\/ICECS.1998.813324"},{"issue":"4","key":"26_CR4","doi-asserted-by":"publisher","first-page":"1898","DOI":"10.1109\/TIE.2007.898283","volume":"54","author":"Y. Fong","year":"2007","unstructured":"Fong, Y., Moallem, M., Wang, W.: Design and Implementation of Modular FPGA-Based PID Controllers. IEEE Trans. on Industrial Electronics\u00a054(4), 1898\u20131906 (2007)","journal-title":"IEEE Trans. on Industrial Electronics"},{"unstructured":"Wittenmark, B., Astrom, K.J., Arzenin, K.E.: Computer control: An overview. Technical Report of Dept. of Automatic Control, Lund Institute of Technology, Lund, Sweden (April 2003), http:\/\/www.control.lth.se\/kursdr\/ifac.pdf","key":"26_CR5"},{"doi-asserted-by":"crossref","unstructured":"Sam, H., Gupta, A.: A Generalized Multibit Recoding of Two\u2019s Complement Binary Numbers and its Proof with Application in Multiplier Implementation. IEEE Trans. on Computers 39(8) (August 1990)","key":"26_CR6","DOI":"10.1109\/12.57039"},{"issue":"2","key":"26_CR7","doi-asserted-by":"publisher","first-page":"148","DOI":"10.1109\/TC.2010.156","volume":"60","author":"F. Lamberti","year":"2011","unstructured":"Lamberti, F.: Reducing the Computation Time in (Short Bit-Width) Two\u2019s Complement Multiplier. IEEE Trans. on Computers\u00a060(2), 148\u2013156 (2011)","journal-title":"IEEE Trans. on Computers"},{"doi-asserted-by":"crossref","unstructured":"Kuang, S.R., Wang, J.P., Guo, C.Y.: Modified Booth Multipliers with a Regular Partial Product Array. IEEE Trans. on Circuit and Systems II, Express Brief 56(5) (May 2009)","key":"26_CR8","DOI":"10.1109\/TCSII.2009.2019334"},{"doi-asserted-by":"crossref","unstructured":"Kang, J.Y., Gaudiot, J.L.: A Simple High-Speed Multiplier Design. IEEE Trans. on Computers 55(10) (October 2006)","key":"26_CR9","DOI":"10.1109\/TC.2006.156"},{"doi-asserted-by":"crossref","unstructured":"Crookes, D., Jiang, M.: Using Signed Digit Arithmetic for Low-Power Multiplication. Electronics Letters 43(11) (May 2007)","key":"26_CR10","DOI":"10.1049\/el:20070761"},{"doi-asserted-by":"crossref","unstructured":"Seidel, P.M., McFearin, L.D., Matula, D.W.: Secondary Radix Recodings for Higher Radix Multipliers. IEEE Trans. on Computers 54(2) (February 2005)","key":"26_CR11","DOI":"10.1109\/TC.2005.32"},{"key":"26_CR12","doi-asserted-by":"publisher","first-page":"219","DOI":"10.1007\/BF00925467","volume":"2","author":"R.C. North","year":"1991","unstructured":"North, R.C., Ku, W.H.: \u03b2-Bit Serial\/Parallel Multipliers. Journal of VLSI Signal Processing\u00a02, 219\u2013233 (1991)","journal-title":"Journal of VLSI Signal Processing"},{"issue":"10","key":"26_CR13","doi-asserted-by":"publisher","first-page":"1014","DOI":"10.1109\/T-C.1975.224114","volume":"24","author":"L.P. Rubinfield","year":"1975","unstructured":"Rubinfield, L.P.: A Proof of the Modified Booth Algorithm for Multiplication. IEEE Trans. On Computers C-24(10), 1014\u20131015 (1975)","journal-title":"IEEE Trans. On Computers C"},{"issue":"2","key":"26_CR14","doi-asserted-by":"publisher","first-page":"542","DOI":"10.1109\/JSSC.1985.1052341","volume":"20","author":"D.A. Henlin","year":"1985","unstructured":"Henlin, D.A., Fertsch, M.T., Mazin, M., Lewis, E.T.: A 16 bit x 16 bit Pipelined Multiplier Marcrocell. IEEE Journal of Solid-State Circuits SC-20(2), 542\u2013547 (1985)","journal-title":"IEEE Journal of Solid-State Circuits SC"},{"doi-asserted-by":"crossref","unstructured":"10. Kelly, J.S., et al.: Design and Implementation of Digital Controllers for Smart Structures Using Field Programmable Gate Arrays. Smart Material Structure Journal, PII: S0964-1726 (97) 87085-1, 559-572 (1997)","key":"#cr-split#-26_CR15.1","DOI":"10.1088\/0964-1726\/6\/5\/007"},{"unstructured":"11. Kelly, J.S., et al.: Design and Implementation of Digital Controllers for Smart Structures Using Field Programmable Gate Arrays. Smart Material Structure Journal, PII: S0964-1726","key":"#cr-split#-26_CR15.2"},{"unstructured":"12. 87085-1, 559-572 (1997); printed in the UK","key":"#cr-split#-26_CR15.3"},{"doi-asserted-by":"crossref","unstructured":"Shang, L., Kaviani, A.S., Bathala, K.: Dynamic Power Consumption in Virtex-II FPGA Family. In: Proceedings of FPGA Conference, Monterey, California, USA, pp. 157\u2013164 (February 2002)","key":"26_CR16","DOI":"10.1145\/503048.503072"},{"unstructured":"Xilinx Inc.: Virtex6 FPGA: Satisfying the Insatiable Demand for Higher Bandwidth. PN 2403, Printed in the USA, Copyright (2009), www.xilinx.com\/publications\/prod_mktg\/Virtex6_Product_Brief.pdf","key":"26_CR17"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-24154-3_26","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,16]],"date-time":"2019-06-16T05:39:18Z","timestamp":1560663558000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-24154-3_26"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642241536","9783642241543"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-24154-3_26","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}