{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T09:06:21Z","timestamp":1725613581894},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642241536"},{"type":"electronic","value":"9783642241543"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-24154-3_9","type":"book-chapter","created":{"date-parts":[[2011,9,23]],"date-time":"2011-09-23T23:38:58Z","timestamp":1316821138000},"page":"83-91","source":"Crossref","is-referenced-by-count":4,"title":["Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS\/Magnetic Technology"],"prefix":"10.1007","author":[{"given":"Gregory","family":"Di Pendina","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kholdoun","family":"Torki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guillaume","family":"Prenat","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yoann","family":"Guillemenet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lionel","family":"Torres","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"9_CR1","doi-asserted-by":"crossref","unstructured":"Hu, Z., Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Jacobson, H., Bose, P.: Microarchitectural techniques for power gating of execution units. In: Proceedings of International Symposiumon Low Power Electronics and Design (ISLPED) (August 2004)","DOI":"10.1145\/1013235.1013249"},{"issue":"1","key":"9_CR2","doi-asserted-by":"publisher","first-page":"301","DOI":"10.1109\/JSSC.2004.837962","volume":"23","author":"T.W. Andre","year":"2005","unstructured":"Andre, T.W., Nahas, J.J., Subramanian, C.K., Garni, B.J., Lin, H.S., Omair, A., Martino, W.L.: A 4-mb 0.18-\u03bcm 1t-1mtj toggle mram with balanced three input sensing scheme and locally mirrored unidirectional write drivers. IEEE Journal of Solid State Circuits\u00a023(1), 301\u2013309 (2005)","journal-title":"IEEE Journal of Solid State Circuits"},{"key":"9_CR3","unstructured":"http:\/\/www.lirmm.fr\/SPIN"},{"issue":"9","key":"9_CR4","doi-asserted-by":"publisher","first-page":"6674","DOI":"10.1063\/1.372806","volume":"87","author":"W.C. Black Jr.","year":"2000","unstructured":"Black Jr., W.C., Das, B.: Programmable logic using giant-magneto-resistance and spindependent tunneling devices. J. Appl. Phys.\u00a087(9), 6674\u20136679 (2000)","journal-title":"J. Appl. Phys."},{"issue":"3","key":"9_CR5","doi-asserted-by":"publisher","first-page":"211","DOI":"10.1049\/iet-cdt.2009.0019","volume":"4","author":"Y. Guillemenet","year":"2010","unstructured":"Guillemenet, Y., Torres, L., Sassatelli, G.: A Non-Volatile Run-Time FPGA structures using Thermally Assisted Switching MRAMs. Journal IET Computers and Digital Techniques\u00a04(3), 211\u2013226 (2010), doi:10.1049\/iet-cdt.2009.0019","journal-title":"Journal IET Computers and Digital Techniques"},{"key":"9_CR6","doi-asserted-by":"crossref","unstructured":"Lakys, Y., Zhao, W., Klein, J.-O., Chappert, C.: Low power, High Reliability Magnetic Flip-Flop. Electronics Letters\u00a046(22), 1493, 2 pages (2010)","DOI":"10.1049\/el.2010.2039"},{"key":"9_CR7","doi-asserted-by":"crossref","unstructured":"Sakimura, N., Sugibayashi, T., Nebashi, R., Kasai, N.: Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs. IEEE Journal of Solid State Circuits\u00a044(8) (August 2009)","DOI":"10.1109\/JSSC.2009.2023192"},{"issue":"12","key":"9_CR8","doi-asserted-by":"publisher","first-page":"2851","DOI":"10.1109\/16.974716","volume":"48","author":"K. Noda","year":"2001","unstructured":"Noda, K., Matsui, K., Takeda, K., Nakamura, N.: A loadless CMOS four-transistor SRAM cell in a 0.18-\u03bcm logic technology. IEEE Transactions on Electron Devices\u00a048(12), 2851\u20132855 (2001), doi:10.1109\/16.974716","journal-title":"IEEE Transactions on Electron Devices"},{"issue":"12","key":"9_CR9","doi-asserted-by":"publisher","first-page":"123906","DOI":"10.1063\/1.3259373","volume":"106","author":"M. ElBaraji","year":"2009","unstructured":"ElBaraji, M., Javerliac, V., Guo, W., Prenat, G., Dieny, B.: Dynamic compact model of thermally assisted switching magnetic tunnel junctions. Journal of Applied Physics\u00a0106(12), 123906 (2009)","journal-title":"Journal of Applied Physics"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-24154-3_9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,16]],"date-time":"2019-06-16T05:38:58Z","timestamp":1560663538000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-24154-3_9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642241536","9783642241543"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-24154-3_9","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}