{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,14]],"date-time":"2025-03-14T01:40:03Z","timestamp":1741916403281,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":32,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642245671"},{"type":"electronic","value":"9783642245688"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-24568-8_11","type":"book-chapter","created":{"date-parts":[[2011,11,14]],"date-time":"2011-11-14T01:01:10Z","timestamp":1321232470000},"page":"215-233","source":"Crossref","is-referenced-by-count":2,"title":["A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture"],"prefix":"10.1007","author":[{"given":"Yasutaka","family":"Wada","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akihiro","family":"Hayashi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takeshi","family":"Masuura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jun","family":"Shirako","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hirofumi","family":"Nakano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroaki","family":"Shikano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Keiji","family":"Kimura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hironori","family":"Kasahara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"11_CR1","doi-asserted-by":"publisher","first-page":"71","DOI":"10.1109\/40.848474","volume":"20","author":"L. Hammond","year":"2000","unstructured":"Hammond, L., Hubbert, B.A., Siu, M., Prabhu, M.K., Chen, M., Olukotun, K.: The stanford hydra CMP. IEEE Micro\u00a020, 71\u201384 (2000)","journal-title":"IEEE Micro"},{"unstructured":"ARM Limited: ARM11 MPCore Processor Technical Reference Manual (2005)","key":"11_CR2"},{"doi-asserted-by":"crossref","unstructured":"Friedrich, J., McCredie, B., James, N., Huott, B., Curran, B., Fluhr, E., Mittal, G., Chan, E., Chan, Y., Plass, D., Chu, S., Le, H., Clark, L., Ripley, J., Taylor, S., Dilullo, J., Lanzerotti, M.: Design of the Power6 microprocessor. In: Digest of Technical Papers of the 2007 IEEE International Solid-State Circuits Conference, pp. 96\u201397 (February 2007)","key":"11_CR3","DOI":"10.1109\/ISSCC.2007.373605"},{"key":"11_CR4","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1109\/MM.2002.997877","volume":"22","author":"M.B. Taylor","year":"2002","unstructured":"Taylor, M.B., Kim, J., Miller, J., Wentzlaff, D., Ghodrat, F., Greenwald, B., Hoffman, H., Johnson, P., Lee, J.W., Lee, W., Ma, A., Saraf, A., Seneski, M., Shnidman, N., Strumpen, V., Frank, M., Amarasinghe, S., Agarwal, A.: The raw microprocessor: A computational fabric for software circuits and general purpose programs. IEEE Micro\u00a022, 25\u201335 (2002)","journal-title":"IEEE Micro"},{"doi-asserted-by":"crossref","unstructured":"Sankaralingam, K., Nagarajan, R., Liu, H., Kim, C., Huh, J., Burger, D., Keckler, S.W., Moore, C.R.: Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture. In: Proceedings of the 30th Annual International Symposium on Computer Architecture, pp. 422\u2013433 (June 2003)","key":"11_CR5","DOI":"10.1145\/859618.859667"},{"doi-asserted-by":"crossref","unstructured":"Shiota, T., Kawasaki, K., Kawabe, Y., Shibamoto, W., Sato, A., Hashimoto, T., Hayakawa, F., Tago, S., Okano, H., Nakamura, Y., Miyake, H., Suga, A., Takahashi, H.: A 51.2GOPS 1.0GB\/s-DMA single-chip multi-processor integrating quadruple 8-Way VLIW processors. In: Digest of Technical Papers of the 2005 IEEE International Solid-State Circuits Conference, pp. 194\u2013593 (February 2005)","key":"11_CR6","DOI":"10.1109\/ISSCC.2005.1493935"},{"doi-asserted-by":"crossref","unstructured":"Sohi, G.S., Breach, S.E., Vijaykumar, T.N.: Multiscalar processors. In: Proceedings of 22nd Annual International Symposium on Computer Architecture, pp. 414\u2013425 (June 1995)","key":"11_CR7","DOI":"10.1145\/223982.224451"},{"doi-asserted-by":"crossref","unstructured":"Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Iyer, P., Singh, A., Jacob, T., Jain, S., Venkataraman, S., Hoskote, Y., Borkar, N.: An 80-Tile 1.28TFLOPS network-on-chip in 65nm CMOS. In: Digest of Technical Papers of the 2007 IEEE International Solid-State Circuits Conference, pp. 98\u2013589 (February 2007)","key":"11_CR8","DOI":"10.1109\/ISSCC.2007.373606"},{"doi-asserted-by":"crossref","unstructured":"Seiler, L., Carmean, D., Sprangle, E., Forsyth, T., Abrash, M., Dubey, P., Junkins, S., Lake, A., Sugerman, J., Cavin, R., Espasa, R., Grochowski, E., Juan, T., Hanrahan, P.: Larrabee: A many-core x86 architecture for visual computing. ACM Transactions on Graphics\u00a027(3) (2008)","key":"11_CR9","DOI":"10.1145\/1360612.1360617"},{"doi-asserted-by":"crossref","unstructured":"Pham, D., Asano, S., Bolliger, M., Day, M.N., Hofstee, H.P., Johns, C., Kahle, J., Kameyama, A., Keaty, J., Masubuchi, Y., Riley, M., Shippy, D., Stasiak, D., Suzuoki, M., Wang, M., Warnock, J., Weitzel, S., Wendel, D., Yamazaki, T., Yazawa, K.: The design and implementation of a first-generation CELL processor. In: Digest of Technical Papers of the 2005 IEEE International Solid-State Circuits Conference, pp. 184\u2013592 (February 2005)","key":"11_CR10","DOI":"10.1109\/ISSCC.2005.1493930"},{"doi-asserted-by":"crossref","unstructured":"Khailany, B., Williams, T., Lin, J., Long, E., Rygh, M., Tovey, D., Dally, W.J.: A programmable 512 GOPS stream processor for signal, image, and video processing. In: Digest of Technical Papers of the 2007 IEEE International Solid-State Circuits Conference, pp. 272\u2013602 (February 2007)","key":"11_CR11","DOI":"10.1109\/ISSCC.2007.373399"},{"doi-asserted-by":"crossref","unstructured":"Torii, S., Suzuki, S., Tomonaga, H., Tokue, T., Sakai, J., Suzuki, N., Murakami, K., Hiraga, T., Shigemoto, K., Tatebe, Y., Ohbuchi, E., Kayama, N., Edahiro, M., Kusano, T., Nishi, N.: A 600MIPS 120mW 70\u03bcA leakage triple-CPU mobile application processor chip. In: Digest of Technical Papers of the 2005 IEEE International Solid-State Circuits Conference, pp. 136\u2013589 (February 2005)","key":"11_CR12","DOI":"10.1109\/ISSCC.2005.1493906"},{"doi-asserted-by":"crossref","unstructured":"Ito, M., Todaka, T., Tsunoda, T., Tanaka, H., Kodama, T., Shikano, H., Onouchi, M., Uchiyama, K., Odaka, T., Kamei, T., Nagahama, E., Kusaoke, M., Nitta, Y., Wada, Y., Kimura, K., Kasahara, H.: Heterogeneous multiprocessor on a chip which enables 54x AAC-LC stereo encoding. In: Proceedings of the 2007 IEEE Symposium on VLSI Circuits, pp. 18\u201319 (June 2007)","key":"11_CR13","DOI":"10.1109\/VLSIC.2007.4342719"},{"doi-asserted-by":"crossref","unstructured":"Kumar, R., Tullsen, D.M., Ranganathan, P., Jouppi, N.P., Farkas, K.I.: Single-ISA heterogeneous multi-core architectures for multithreaded workload performance. In: Proceedings of the 31st Annual International Symposium on Computer Architecture, pp. 64\u201375 (June 2004)","key":"11_CR14","DOI":"10.1109\/ISCA.2004.1310764"},{"unstructured":"Shikano, H., Suzuki, Y., Wada, Y., Shirako, J., Kimura, K., Kasahara, H.: Performance evaluation of heterogeneous chip multi-processor with MP3 audio encoder. In: Proceedings of the IEEE Symposium on Low-Power and High Speed Chips, pp. 349\u2013363 (April 2006)","key":"11_CR15"},{"doi-asserted-by":"crossref","unstructured":"Noda, H., Tanizaki, T., Gyohten, T., Dosaka, K., Nakajima, M., Mizumoto, K., Yoshida, K., Iwao, T., Nishijima, T., Okuno, Y., Arimoto, K.: The circuits and robust design methodology of the massively parallel processor based on the matrix architecture. In: Digest of Technical Papers of the 2006 Symposium on VLSI Circuits, pp. 210\u2013211 (2006)","key":"11_CR16","DOI":"10.1109\/VLSIC.2006.1705384"},{"unstructured":"NVIDIA Corporation: NVIDIA CUDA Compute Unified Device Architecture Programming Guide (2008)","key":"11_CR17"},{"doi-asserted-by":"crossref","unstructured":"Xie, T., Qin, X.: Stochastic scheduling with availability constraints in heterogeneous clusters. In: Proceedings of the 2006 IEEE International Conference on Cluster Computing, pp. 1\u201310 (September 2006)","key":"11_CR18","DOI":"10.1109\/CLUSTR.2006.311866"},{"key":"11_CR19","doi-asserted-by":"publisher","first-page":"175","DOI":"10.1109\/71.207593","volume":"4","author":"G.C. Sih","year":"1993","unstructured":"Sih, G.C., Lee, E.A.: A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures. IEEE Transactions on Parallel and Distributed Systems\u00a04, 175\u2013187 (1993)","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"unstructured":"Chan, W.Y., Li, C.K.: Scheduling tasks in DAG to heterogeneous processor system. In: Proceedings of the 6th Euromicro Workshop on Parallel and Distributed Processing, pp. 27\u201331 (January 1998)","key":"11_CR20"},{"key":"11_CR21","doi-asserted-by":"publisher","first-page":"260","DOI":"10.1109\/71.993206","volume":"13","author":"H. Topcuoglu","year":"2002","unstructured":"Topcuoglu, H., Hariri, S., Wu, M.Y.: Performance-effective and low-complexity task scheduling for heterogeneous computing. IEEE Transactions on Parallel and Distributed Systems\u00a013, 260\u2013274 (2002)","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"doi-asserted-by":"crossref","unstructured":"Kasahara, H., Honda, H., Narita, S.: Parallel processing of near fine grain tasks using static scheduling on OSCAR (Optimally SCheduled Advanced multiprocessoR). In: Proceedings of Supercomputing \u201990, pp. 856\u2013864 (November 1990)","key":"11_CR22","DOI":"10.1109\/SUPERC.1990.130111"},{"doi-asserted-by":"crossref","unstructured":"Kimura, K., Kodaka, T., Obata, M., Kasahara, H.: Multigrain parallel processing on OSCAR CMP. In: Proceedings of the 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (January 2003)","key":"11_CR23","DOI":"10.1109\/IWIA.2003.1262783"},{"doi-asserted-by":"crossref","unstructured":"Ishizaka, K., Miyamoto, T., Shirako, J., Obata, M., Kimura, K., Kasahara, H.: Performance of OSCAR multigrain parallelizing compiler on SMP servers. In: Proceedings of the 17th International Workshop on Languages and Compilers for Parallel Computing (September 2004)","key":"11_CR24","DOI":"10.1007\/11532378_23"},{"doi-asserted-by":"crossref","unstructured":"Kimura, K., Wada, Y., Nakano, H., Kodaka, T., Shirako, J., Ishizaka, K., Kasahara, H.: Multigrain parallel processing on compiler cooperative chip multiprocessor. In: Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures, pp. 11\u201320 (February 2005)","key":"11_CR25","DOI":"10.1109\/INTERACT.2005.9"},{"doi-asserted-by":"crossref","unstructured":"Kasahara, H., Ogata, W., Kimura, K., Matsui, G., Matsuzaki, H., Okamoto, M., Yoshida, A., Honda, H.: OSCAR multi-grain architecture and its evaluation. In: Proceedings of the 1997 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, pp. 106\u2013115 (October 1997)","key":"11_CR26","DOI":"10.1109\/IWIA.1997.670416"},{"doi-asserted-by":"crossref","unstructured":"Kasahara, H., Honda, H., Mogi, A., Ogura, A., Fujiwara, K., Narita, S.: A multi-grain parallelizing compilation scheme for OSCAR (Optimally scheduled advanced multiprocessor). In: Proceedings of the Fourth International Workshop on Languages and Compilers for Parallel Computing, pp. 283\u2013297 (August 1991)","key":"11_CR27","DOI":"10.1007\/BFb0038671"},{"key":"11_CR28","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"31","DOI":"10.1007\/11596110_3","volume-title":"Languages and Compilers for Parallel Computing","author":"M. Obata","year":"2005","unstructured":"Obata, M., Shirako, J., Kaminaga, H., Ishizaka, K., Kasahara, H.: Hierarchical parallelism control for multigrain parallel processing. In: Pugh, B., Tseng, C.-W. (eds.) LCPC 2002. LNCS, vol.\u00a02481, pp. 31\u201344. Springer, Heidelberg (2005)"},{"unstructured":"Shirako, J., Nagasawa, K., Ishizaka, K., Obata, M., Kasahara, H.: Selective inline expansion for improvement of multi grain parallelism. In: The IASTED International Conference on Parallel and Distributed Computing and Networks, pp. 128\u2013134 (February 2004)","key":"11_CR29"},{"doi-asserted-by":"crossref","unstructured":"Yoshida, Y., Kamei, T., Hayase, K., Shibahara, S., Nishii, O., Hattori, T., Hasegawa, A., Takada, M., Irie, N., Uchiyama, K., Odaka, T., Takada, K., Kimura, K., Kasahara, H.: A 4320MIPS four-processor core SMP\/AMP with individually managed clock frequency for low power consumption. In: Digest of Technical Papers of the 2007 IEEE International Solid-State Circuits Conference, pp. 100\u2013590 (February 2007)","key":"11_CR30","DOI":"10.1109\/ISSCC.2007.373607"},{"unstructured":"Kodama, T., Tsunoda, T., Takada, M., Tanaka, H., Akita, Y., Sato, M., Ito, M.: Flexible engine: A dynamic reconfigurable accelerator with high performance and low power consumption. In: Proceedings of the IEEE Symposium on Low-Power and High Speed Chips, pp. 393\u2013408 (April 2006)","key":"11_CR31"},{"unstructured":"UZURA3: MPEG1\/LayerIII encoder in FORTRAN90, http:\/\/members.at.infoseek.co.jp\/kitaurawa\/index_e.html","key":"11_CR32"}],"container-title":["Lecture Notes in Computer Science","Transactions on High-Performance Embedded Architectures and Compilers IV"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-24568-8_11","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,14]],"date-time":"2025-03-14T01:22:07Z","timestamp":1741915327000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-24568-8_11"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642245671","9783642245688"],"references-count":32,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-24568-8_11","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}