{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T14:38:18Z","timestamp":1725633498206},"publisher-location":"Berlin, Heidelberg","reference-count":27,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642245671"},{"type":"electronic","value":"9783642245688"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-24568-8_18","type":"book-chapter","created":{"date-parts":[[2011,11,13]],"date-time":"2011-11-13T20:01:10Z","timestamp":1321214470000},"page":"354-369","source":"Crossref","is-referenced-by-count":0,"title":["Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation"],"prefix":"10.1007","author":[{"given":"W. G.","family":"Osborne","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"W.","family":"Luk","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J. G. F.","family":"Coutinho","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"O.","family":"Mencer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"2","key":"18_CR1","doi-asserted-by":"publisher","first-page":"203","DOI":"10.1109\/TCAD.2006.884574","volume":"26","author":"I. Kuon","year":"2007","unstructured":"Kuon, I., Rose, J.: Measuring the gap between FPGAs and ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a026(2), 203\u2013215 (2007)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"2","key":"18_CR2","doi-asserted-by":"publisher","first-page":"438","DOI":"10.1109\/JPROC.2006.888404","volume":"95","author":"J. Becker","year":"2007","unstructured":"Becker, J., H\u00fcbner, M., Hettich, G., Constapel, R., Eisenmann, J., Luka, J.: Dynamic and partial FPGA exploitation. Proceedings of the IEEE\u00a095(2), 438\u2013452 (2007)","journal-title":"Proceedings of the IEEE"},{"key":"18_CR3","doi-asserted-by":"publisher","first-page":"318","DOI":"10.1109\/FPGA.2002.1106699","volume-title":"Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines","author":"T. Courtney","year":"2002","unstructured":"Courtney, T., Turner, R., Woods, R.: Mapping multi-mode circuits to LUT-based FPGA using embedded MUXes. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 318\u2013327. IEEE Computer Society Press, Los Alamitos (2002)"},{"key":"18_CR4","first-page":"167","volume-title":"Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines","author":"W. Luk","year":"1996","unstructured":"Luk, W., Shirazi, N., Cheung, P.Y.K.: Modelling and optimising run-time reconfigurable systems. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 167\u2013176. IEEE Computer Society Press, Los Alamitos (1996)"},{"key":"18_CR5","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"972","DOI":"10.1007\/978-3-540-45234-8_98","volume-title":"Field Programmable Logic and Application","author":"R.H. Turner","year":"2003","unstructured":"Turner, R.H., Woods, R.F.: Design flow for efficient FPGA reconfiguration. In: Cheung, P.Y.K., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol.\u00a02778, pp. 972\u2013975. Springer, Heidelberg (2003)"},{"key":"18_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"66","DOI":"10.1007\/3-540-58419-6_70","volume-title":"Field-Programmable Logic: Architectures, Synthesis and Applications","author":"A.H. Farrahi","year":"1994","unstructured":"Farrahi, A.H., Sarrafzadeh, M.: FPGA technology mapping for power minimization. In: Hartenstein, R.W., Servit, M.Z. (eds.) FPL 1994. LNCS, vol.\u00a0849, pp. 66\u201377. Springer, Heidelberg (1994)"},{"key":"18_CR7","unstructured":"Klein, M.: Power considerations in 90nm FPGA designs. Xcell Journal (Fourth Quarter), 56\u201359 (2005)"},{"key":"18_CR8","unstructured":"Stephenson, J.: Design guidelines for optimal results in FPGAs. Altera (2005), \n                    \n                      http:\/\/www.altera.com\/literature\/cp\/fpgas-optimal-results-396.pdf"},{"key":"18_CR9","doi-asserted-by":"crossref","unstructured":"Zhang, Y., Roivainen, J., M\u00e4mmel\u00e4, A.: Clock-gating in FPGAs: A novel and comparative evaluation. In: Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, pp. 584\u2013590 (August 2006)","DOI":"10.1109\/DSD.2006.32"},{"key":"18_CR10","first-page":"1226","volume-title":"Proceedings of the 5th International Conference on ASIC","author":"O. Cadenas","year":"2003","unstructured":"Cadenas, O., Megson, G.: Power performance with gated clocks of a pipelined Cordic core. In: Proceedings of the 5th International Conference on ASIC, vol.\u00a02, pp. 1226\u20131230. IEEE, Los Alamitos (2003)"},{"key":"18_CR11","first-page":"187","volume-title":"Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation","author":"W.G. Osborne","year":"2008","unstructured":"Osborne, W.G., Luk, W., Coutinho, J.G.F., Mencer, O.: Reconfigurable design with clock gating. In: Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, pp. 187\u2013194. IEEE, Los Alamitos (2008)"},{"issue":"2","key":"18_CR12","doi-asserted-by":"publisher","first-page":"89","DOI":"10.1145\/350853.350856","volume":"18","author":"D. Brooks","year":"2000","unstructured":"Brooks, D., Martonosi, M.: Value-based clock gating and operation packing: Dynamic strategies for improving processor power and performance. ACM Transactions on Computer Systems\u00a018(2), 89\u2013126 (2000)","journal-title":"ACM Transactions on Computer Systems"},{"issue":"1","key":"18_CR13","doi-asserted-by":"publisher","first-page":"75","DOI":"10.1023\/A:1021193802261","volume":"33","author":"V.G. Moshnyaga","year":"2003","unstructured":"Moshnyaga, V.G.: Reducing switching activity of subtraction via variable truncation of the most-significant bits. Journal of VLSI Signal Processing Systems\u00a033(1), 75\u201382 (2003)","journal-title":"Journal of VLSI Signal Processing Systems"},{"issue":"11","key":"18_CR14","doi-asserted-by":"publisher","first-page":"1408","DOI":"10.1109\/TC.2004.96","volume":"53","author":"H. Styles","year":"2004","unstructured":"Styles, H., Luk, W.: Exploiting program branch probabilities in hardware compilation. IEEE Transactions on Computers\u00a053(11), 1408\u20131419 (2004)","journal-title":"IEEE Transactions on Computers"},{"key":"18_CR15","first-page":"249","volume-title":"Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines","author":"K. Bondalapati","year":"1999","unstructured":"Bondalapati, K., Prasanna, V.K.: Dynamic precision management for loop computations on reconfigurable architectures. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 249\u2013258. IEEE Computer Society Press, Los Alamitos (1999)"},{"issue":"10","key":"18_CR16","doi-asserted-by":"publisher","first-page":"1990","DOI":"10.1109\/TCAD.2006.873887","volume":"25","author":"D. Lee","year":"2006","unstructured":"Lee, D., Abdul Gaffar, A., Cheung, R.C.C., Mencer, O., Luk, W., Constantinides, G.A.: Accuracy-guaranteed bit-width optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a025(10), 1990\u20132000 (2006)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"18_CR17","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"57","DOI":"10.1007\/11925040_5","volume-title":"Leveraging Applications of Formal Methods","author":"D.J. Quinlan","year":"2006","unstructured":"Quinlan, D.J., Schordan, M., Yi, Q., Saebjornsen, A.: Classification and utilization of abstractions for optimization. In: Margaria, T., Steffen, B. (eds.) ISoLA 2004. LNCS, vol.\u00a04313, pp. 57\u201373. Springer, Heidelberg (2006)"},{"key":"18_CR18","first-page":"56","volume-title":"Proceedings IEEE Symposium on Field-Programmable Custom Computing Machines","author":"W. Luk","year":"1997","unstructured":"Luk, W., Shirazi, N., Cheung, P.Y.K.: Compilation tools for run-time reconfigurable designs. In: Proceedings IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 56\u201365. IEEE Computer Society Press, Los Alamitos (1997)"},{"key":"18_CR19","first-page":"147","volume-title":"Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines","author":"N. Shirazi","year":"1998","unstructured":"Shirazi, N., Luk, W., Cheung, P.Y.K.: Automating production of run-time reconfigurable designs. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 147\u2013156. IEEE Computer Society Press, Los Alamitos (1998)"},{"key":"18_CR20","first-page":"35","volume-title":"Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines","author":"T. Becker","year":"2007","unstructured":"Becker, T., Luk, W., Cheung, P.Y.K.: Enhancing relocatability of partial bitstreams for run-time reconfiguration. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 35\u201344. IEEE Computer Society Press, Los Alamitos (2007)"},{"key":"18_CR21","doi-asserted-by":"publisher","first-page":"173","DOI":"10.1145\/1150343.1150389","volume-title":"Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design","author":"K. Paulsson","year":"2006","unstructured":"Paulsson, K., H\u00fcbner, M., Becker, J.: On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, pp. 173\u2013178. ACM, New York (2006)"},{"key":"18_CR22","first-page":"77","volume-title":"Proceedings of the 5th Southern Conference on Programmable Logic","author":"T. Becker","year":"2009","unstructured":"Becker, T., Jamieson, P., Luk, W., Cheung, P.Y.K., Rissa, T.: Power characterisation for the fabric in fine-grain reconfigurable architectures. In: Proceedings of the 5th Southern Conference on Programmable Logic, pp. 77\u201382. IEEE, Los Alamitos (2009)"},{"key":"18_CR23","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"842","DOI":"10.1007\/978-3-540-30117-2_86","volume-title":"Field Programmable Logic and Application","author":"B. Griese","year":"2004","unstructured":"Griese, B., Vonnahme, E., Porrmann, M., R\u00fcckert, U.: Hardware support for dynamic reconfiguration in reconfigurable SoC architectures. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol.\u00a03203, pp. 842\u2013846. Springer, Heidelberg (2004)"},{"key":"18_CR24","first-page":"283","volume-title":"Proceedings of the 16th Symposium on Integrated Circuits and Systems Design","author":"J. Becker","year":"2003","unstructured":"Becker, J., H\u00fcbner, M., Ullmann, M.: Power estimation and power measurement of Xilinx Virtex FPGAs: Trade-offs and limitations. In: Proceedings of the 16th Symposium on Integrated Circuits and Systems Design, pp. 283\u2013288. IEEE Computer Society, Los Alamitos (2003)"},{"key":"18_CR25","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"1057","DOI":"10.1007\/978-3-540-45234-8_119","volume-title":"Field Programmable Logic and Application","author":"J. Jiang","year":"2003","unstructured":"Jiang, J., Luk, W., Rueckert, D.: FPGA-based computation of free-form deformations. In: Cheung, P.Y.K., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol.\u00a02778, pp. 1057\u20131061. Springer, Heidelberg (2003)"},{"key":"18_CR26","first-page":"311","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications","author":"H. Styles","year":"2005","unstructured":"Styles, H., Luk, W.: Compilation and management of phase-optimized reconfigurable systems. In: Proceedings of the International Conference on Field Programmable Logic and Applications, pp. 311\u2013316. IEEE, Los Alamitos (2005)"},{"key":"18_CR27","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"719","DOI":"10.1007\/978-3-540-30117-2_73","volume-title":"Field Programmable Logic and Application","author":"S.J. Wilton","year":"2004","unstructured":"Wilton, S.J., Ang, S.S., Luk, W.: The impact of pipelining on energy per operation in Field-Programmable Gate Arrays. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol.\u00a03203, pp. 719\u2013728. Springer, Heidelberg (2004)"}],"container-title":["Lecture Notes in Computer Science","Transactions on High-Performance Embedded Architectures and Compilers IV"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-24568-8_18","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,17]],"date-time":"2019-04-17T06:21:42Z","timestamp":1555482102000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-24568-8_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642245671","9783642245688"],"references-count":27,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-24568-8_18","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}