{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T14:38:29Z","timestamp":1725633509135},"publisher-location":"Berlin, Heidelberg","reference-count":42,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642245671"},{"type":"electronic","value":"9783642245688"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-24568-8_8","type":"book-chapter","created":{"date-parts":[[2011,11,13]],"date-time":"2011-11-13T20:01:10Z","timestamp":1321214470000},"page":"155-174","source":"Crossref","is-referenced-by-count":0,"title":["Finding Extreme Behaviors in Microprocessor Workloads"],"prefix":"10.1007","author":[{"given":"Frederik","family":"Vandeputte","sequence":"first","affiliation":[]},{"given":"Lieven","family":"Eeckhout","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"8_CR1","unstructured":"Felter, W., Keller, T.: Power measurement on the Apple Power Mac G5. Technical Report RC23276, IBM (2004)"},{"key":"8_CR2","doi-asserted-by":"crossref","unstructured":"Gowan, M.K., Biro, L.L., Jackson, D.B.: Power considerations in the design of the Alpha 21264 microprocessor. In: Proceedings of the 35th Design Automation Conference (DAC), pp. 726\u2013731 (June 1998)","DOI":"10.1145\/277044.277226"},{"key":"8_CR3","unstructured":"Vishmanath, R., Wakharkar, V., Watwe, A., Lebonheur, V.: Thermal performance challenges from silicon to systems. Intel Technology Journal\u00a04(3) (August 2000)"},{"key":"8_CR4","doi-asserted-by":"crossref","unstructured":"Joseph, R., Brooks, D., Martonosi, M.: Control techniques to eliminate voltage emergencies in high performance processors. In: Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), pp. 79\u201390 (February 2003)","DOI":"10.1109\/HPCA.2003.1183526"},{"key":"8_CR5","doi-asserted-by":"crossref","unstructured":"Brooks, D., Martonosi, M.: Dynamic thermal management for high-performance microprocessors. In: Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA), pp. 171\u2013182 (January 2001)","DOI":"10.1109\/HPCA.2001.903261"},{"key":"8_CR6","doi-asserted-by":"crossref","unstructured":"Skadron, K., Stan, M.R., Huang, W., Velusamy, S., Sankaranarayanan, K., Tarjan, D.: Temperature-aware microarchitecture. In: Proceedings of the International Symposium on Computer Architecture (ISCA), pp. 2\u201313 (June 2003)","DOI":"10.1145\/859618.859620"},{"key":"8_CR7","unstructured":"Gunther, S.H., Binns, F., Carmean, D.M., Hall, J.C.: Managing the impact of increasing microprocessor power consumption. Intel Journal of Technology\u00a05(1) (February 2001)"},{"key":"8_CR8","doi-asserted-by":"crossref","unstructured":"Tiwari, V., Singh, D., Rajgopal, S., Mehta, G., Patel, R., Baez, F.: Reducing power in high-performance microprocessors. In: Proceedings of the Design Automation Conference (DAC), pp. 732\u2013737 (June 1998)","DOI":"10.1145\/277044.277227"},{"key":"8_CR9","doi-asserted-by":"crossref","unstructured":"Wunderlich, R.E., Wenisch, T.F., Falsafi, B., Hoe, J.C.: SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling. In: Proceedings of the Annual International Symposium on Computer Architecture (ISCA), pp. 84\u201395 (June 2003)","DOI":"10.1145\/859618.859629"},{"key":"8_CR10","doi-asserted-by":"crossref","unstructured":"Sherwood, T., Perelman, E., Hamerly, G., Calder, B.: Automatically characterizing large scale program behavior. In: Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 45\u201357 (October 2002)","DOI":"10.1145\/605397.605403"},{"key":"8_CR11","unstructured":"Yi, J.J., Kodakara, S.V., Sendag, R., Lilja, D.J., Hawkins, D.M.: Characterizing and comparing prevailing simulation techniques. In: Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), pp. 266\u2013277 (February 2005)"},{"key":"8_CR12","doi-asserted-by":"crossref","unstructured":"Vandeputte, F., Eeckhout, L.: Finding stress patterns in microprocessor workloads. In: Proceedings of the 2009 International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), pp. 153\u2013167 (January 2009)","DOI":"10.1007\/978-3-540-92990-1_13"},{"key":"8_CR13","unstructured":"(SPEC), S.P.E.C.: Specpower_ssj2008, http:\/\/www.spec.org\/power_ssj2008\/"},{"key":"8_CR14","unstructured":"Kanter, D.: EEMBC energizes benchmarking. Microprocessor Report (July 2006)"},{"key":"8_CR15","doi-asserted-by":"crossref","unstructured":"Van Biesbrouck, M., Eeckhout, L., Calder, B.: Efficient sampling startup for sampled processor simulation. In: 2005 International Conference on High Performance Embedded Architectures and Compilation (HiPEAC), pp. 47\u201367 (November 2005)","DOI":"10.1007\/11587514_5"},{"key":"8_CR16","doi-asserted-by":"crossref","unstructured":"Wenisch, T.F., Wunderlich, R.E., Falsafi, B., Hoe, J.C.: Simulation sampling with live-points. In: Proceedings of the Annual International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 2\u201312 (March 2006)","DOI":"10.1109\/ISPASS.2006.1620785"},{"key":"8_CR17","doi-asserted-by":"crossref","unstructured":"Conte, T.M., Hirsch, M.A., Menezes, K.N.: Reducing state loss for effective trace sampling of superscalar processors. In: Proceedings of the International Conference on Computer Design (ICCD), pp. 468\u2013477 (October 1996)","DOI":"10.1109\/ICCD.1996.563595"},{"issue":"4","key":"8_CR18","doi-asserted-by":"publisher","first-page":"451","DOI":"10.1093\/comjnl\/bxh103","volume":"48","author":"L. Eeckhout","year":"2005","unstructured":"Eeckhout, L., Luo, Y., De Bosschere, K., John, L.K.: BLRL: Accurate and efficient warmup for sampled processor simulation. The Computer Journal\u00a048(4), 451\u2013459 (2005)","journal-title":"The Computer Journal"},{"issue":"1","key":"8_CR19","doi-asserted-by":"publisher","first-page":"78","DOI":"10.1145\/1061267.1061272","volume":"2","author":"J.W. Haskins Jr.","year":"2005","unstructured":"Haskins Jr., J.W., Skadron, K.: Accelerated warmup for sampled microarchitecture simulation. ACM Transactions on Architecture and Code Optimization (TACO)\u00a02(1), 78\u2013108 (2005)","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"},{"key":"8_CR20","doi-asserted-by":"crossref","unstructured":"Kluyskens, S., Eeckhout, L.: Branch history matching: Branch predictor warmup for sampled simulation. In: Proceedings of the Second International Conference on High Performance Embedded Architectures and Compilation (HiPEAC), pp. 153\u2013167 (January 2007)","DOI":"10.1007\/978-3-540-69338-3_11"},{"issue":"11","key":"8_CR21","doi-asserted-by":"publisher","first-page":"1325","DOI":"10.1109\/12.8699","volume":"37","author":"S. Laha","year":"1988","unstructured":"Laha, S., Patel, J.H., Iyer, R.K.: Accurate low-cost methods for performance evaluation of cache memory systems. IEEE Transactions on Computers\u00a037(11), 1325\u20131336 (1988)","journal-title":"IEEE Transactions on Computers"},{"key":"8_CR22","unstructured":"Dubey, P.K., Nair, R.: Profile-driven sampled trace generation. Technical Report RC 20041, IBM Research Division, T. J. Watson Research Center (April 1995)"},{"key":"8_CR23","doi-asserted-by":"crossref","unstructured":"Iyengar, V.S., Trevillyan, L.H., Bose, P.: Representative traces for processor models with infinite cache. In: Proceedings of the Second International Symposium on High-Performance Computer Architecture (HPCA), pp. 62\u201373 (February 1996)","DOI":"10.1109\/HPCA.1996.501174"},{"key":"8_CR24","doi-asserted-by":"crossref","unstructured":"Lafage, T., Seznec, A.: Choosing representative slices of program execution for microarchitecture simulations: A preliminary application to the data stream. In: IEEE 3rd Annual Workshop on Workload Characterization (WWC-2000) Held in Conjunction with the International Conference on Computer Design (ICCD (September 2000)","DOI":"10.1007\/978-1-4615-1613-2_7"},{"key":"8_CR25","doi-asserted-by":"crossref","unstructured":"Lauterbach, G.: Accelerating architectural simulation by parallel execution of trace samples. Technical Report SMLI TR-93-22, Sun Microsystems Laboratories Inc. (December 1993)","DOI":"10.1109\/HICSS.1994.323171"},{"issue":"11","key":"8_CR26","doi-asserted-by":"publisher","first-page":"1260","DOI":"10.1109\/12.811115","volume":"48","author":"K. Skadron","year":"1999","unstructured":"Skadron, K., Ahuja, P.S., Martonosi, M., Clark, D.W.: Branch prediction, instruction-window size, and cache size: Performance tradeoffs and simulation techniques. IEEE Transactions on Computers\u00a048(11), 1260\u20131281 (1999)","journal-title":"IEEE Transactions on Computers"},{"key":"8_CR27","doi-asserted-by":"crossref","unstructured":"Sherwood, T., Perelman, E., Calder, B.: Basic block distribution analysis to find periodic behavior and simulation points in applications. In: Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 3\u201314 (September 2001)","DOI":"10.1109\/PACT.2001.953283"},{"key":"8_CR28","doi-asserted-by":"crossref","unstructured":"Lau, J., Sampson, J., Perelman, E., Hamerly, G., Calder, B.: The strong correlation between code signatures and performance. In: Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 236\u2013247 (March 2005)","DOI":"10.1109\/ISPASS.2005.1430578"},{"key":"8_CR29","doi-asserted-by":"crossref","unstructured":"Burger, D.C., Austin, T.M.: The SimpleScalar Tool Set. Computer Architecture News (1997), http:\/\/www.simplescalar.com","DOI":"10.1145\/268806.268810"},{"key":"8_CR30","doi-asserted-by":"crossref","unstructured":"Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA), pp. 83\u201394 (June 2000)","DOI":"10.1145\/339647.339657"},{"key":"8_CR31","unstructured":"Hamerly, G., Perelman, E., Lau, J., Calder, B.: SimPoint 3.0: Faster and more flexible program analysis. Journal of Instruction-Level Parallelism\u00a07 (September 2005)"},{"issue":"3","key":"8_CR32","doi-asserted-by":"publisher","first-page":"369","DOI":"10.1109\/92.532037","volume":"4","author":"T. Chou","year":"1996","unstructured":"Chou, T., Roy, K.: Accurate power estimation of CMOS sequential circuits. IEEE Transaction on VLSI Systems\u00a04(3), 369\u2013380 (1996)","journal-title":"IEEE Transaction on VLSI Systems"},{"key":"8_CR33","doi-asserted-by":"crossref","unstructured":"Srinivasan, V., Brooks, D., Gschwind, M., Bose, P., Zyuban, V., Strenski, P.N., Emma, P.G.: Optimizing pipelines for power and performance. In: Proceedings of the 35th Annual International Symposium on Microarchitecture (MICRO), pp. 333\u2013344 (November 2002)","DOI":"10.1109\/MICRO.2002.1176261"},{"key":"8_CR34","doi-asserted-by":"crossref","unstructured":"Joshi, A.M., Eeckhout, L., John, L.K., Isen, C.: Automated microprocessor stressmark generation. In: Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), pp. 229\u2013239 (February 2008)","DOI":"10.1109\/HPCA.2008.4658642"},{"key":"8_CR35","doi-asserted-by":"crossref","unstructured":"Dhodapkar, A., Smith, J.E.: Managing multi-configuration hardware via dynamic working set analysis. In: Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA), pp. 233\u2013244 (May 2002)","DOI":"10.1109\/ISCA.2002.1003581"},{"key":"8_CR36","doi-asserted-by":"crossref","unstructured":"Dhodapkar, A.S., Smith, J.E.: Comparing program phase detection techniques. In: Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), pp. 217\u2013227 (December 2003)","DOI":"10.1109\/MICRO.2003.1253197"},{"key":"8_CR37","doi-asserted-by":"crossref","unstructured":"Sherwood, T., Sair, S., Calder, B.: Phase tracking and prediction. In: Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), pp. 336\u2013347 (June 2003)","DOI":"10.1145\/859654.859657"},{"key":"8_CR38","doi-asserted-by":"crossref","unstructured":"Huang, M., Renau, J., Torrellas, J.: Positional adaptation of processors: Application to energy reduction. In: Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), pp. 157\u2013168 (June 2003)","DOI":"10.1145\/859618.859637"},{"key":"8_CR39","doi-asserted-by":"crossref","unstructured":"Duesterwald, E., Cascaval, C., Dwarkadas, S.: Characterizing and predicting program behavior and its variability. In: Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 220\u2013231 (October 2003)","DOI":"10.1109\/PACT.2003.1238018"},{"key":"8_CR40","doi-asserted-by":"crossref","unstructured":"Isci, C., Martonosi, M.: Identifying program power phase behavior using power vectors. In: Proceedings of the Sixth Annual IEEE International Workshop on Workload Characterization (WWC) (September 2003)","DOI":"10.1109\/WWC.2003.1249062"},{"key":"8_CR41","doi-asserted-by":"crossref","unstructured":"Isci, C., Martonosi, M.: Runtime power monitoring in high-end processors: Methodology and empirical data. In: Proceedings of the 36th Annual International Symposium on Microarchitecture (MICRO), pp. 93\u2013104 (December 2003)","DOI":"10.1109\/MICRO.2003.1253186"},{"key":"8_CR42","doi-asserted-by":"crossref","unstructured":"Isci, C., Martonosi, M.: Phase characterization for power: Evaluating control-flow-based and event-counter-based techniques. In: Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), pp. 122\u2013133 (February 2006)","DOI":"10.1109\/HPCA.2006.1598119"}],"container-title":["Lecture Notes in Computer Science","Transactions on High-Performance Embedded Architectures and Compilers IV"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-24568-8_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,19]],"date-time":"2019-06-19T09:38:34Z","timestamp":1560937114000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-24568-8_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642245671","9783642245688"],"references-count":42,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-24568-8_8","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}