{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,14]],"date-time":"2025-03-14T04:10:32Z","timestamp":1741925432530,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642246494"},{"type":"electronic","value":"9783642246500"}],"license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-3-642-24650-0_9","type":"book-chapter","created":{"date-parts":[[2011,10,22]],"date-time":"2011-10-22T14:08:55Z","timestamp":1319292535000},"page":"93-105","source":"Crossref","is-referenced-by-count":0,"title":["Compiler Support for Concurrency Synchronization"],"prefix":"10.1007","author":[{"given":"Tzong-Yen","family":"Lin","sequence":"first","affiliation":[]},{"given":"Cheng-Yu","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Chia-Jung","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Rong-Guey","family":"Chang","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"9_CR1","doi-asserted-by":"crossref","unstructured":"Magnusson, P.S., et al.: Simics: A full system simulation platform. IEEE Computer, 50\u201358 (February 2002)","DOI":"10.1109\/2.982916"},{"key":"9_CR2","doi-asserted-by":"crossref","unstructured":"Ananian, C.S., Asanovic, K., Kuszmaul, B.C., Leiserson, C.E., Lie, S.: Unbounded transactional memory. In: Proceedings of the 11th International Symposium on High-Performance Computer Architecture, pp. 316\u2013327 (January 2005)","DOI":"10.1109\/HPCA.2005.41"},{"key":"9_CR3","doi-asserted-by":"crossref","unstructured":"Blasgen, M., Gray, J., Mitoma, M., Price, T.: The convoy phenomenon. SIGOPS Oper. Syst. Rev. 20\u201325 (1979)","DOI":"10.1145\/850657.850659"},{"key":"9_CR4","doi-asserted-by":"crossref","unstructured":"Bobba, J., Moore, K.E., Volos, H., Yen, L., Hill, M.D., Swiftand, M.M., Wood, D.A.: Performance pathologies in hardware transactional memory. In: Proceedings of the 34th Annual International Symposium on Computer Architecture, pp. 387\u2013394 (June 2007)","DOI":"10.1145\/1250662.1250674"},{"key":"9_CR5","doi-asserted-by":"crossref","unstructured":"Carlstrom, B.D., McDonald, A., Chafi, H., Chung, J., Minh, C.C., Kozyrakis, C., Olukotun, K.: The atomo\u03c3 transactional programming language. In: Proceedings of the 2006 ACM SIGPLAN Conference on Programming Language Design and Implementation (June 2006)","DOI":"10.1145\/1133981.1133983"},{"key":"9_CR6","doi-asserted-by":"crossref","unstructured":"Ceze, L., Tuck, J., Cascaval, C., Torrellas, J.: Bulk disambiguation of speculative threads in multiprocessors. In: Proceedings of the 33rd Annual International Symposium on Computer Architecture (June 2006)","DOI":"10.1109\/ISCA.2006.13"},{"key":"9_CR7","doi-asserted-by":"crossref","unstructured":"Courtois, P.J., Heymans, F., Parnas, D.L.: Concurrent control with readers and writers. Communications of the ACM, 667\u2013668 (1971)","DOI":"10.1145\/362759.362813"},{"key":"9_CR8","doi-asserted-by":"crossref","unstructured":"Damron, P., Fedorova, A., Lev, Y., Luchango, V., Moir, M., Nussbaum, D.: Hybrid transactional memory. In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (October 2006)","DOI":"10.1145\/1168857.1168900"},{"key":"9_CR9","unstructured":"Gottschlich, J., Connors, D.A.: Extending contention managers for user-defined priority-based transactions. In: Proceedings of the 2008 Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (April 2008)"},{"key":"9_CR10","doi-asserted-by":"crossref","unstructured":"Hammond, L., Wong, V., Chen, M., Carlstrom, B.D., Davis, J.D., Hertzberg, B., Prabhu, M.K., Wijaya, H., Kozyrakis, C., Olukotun, K.: Transactional memory coherence and consistencys. In: Proceedings of the 31st Annual International Symposium on Computer Architecture (June 2004)","DOI":"10.1109\/ISCA.2004.1310767"},{"key":"9_CR11","doi-asserted-by":"crossref","unstructured":"Herlihy, M., Moss, J.E.B.: Transactional memory: Architectural support for lock-free data structures. In: Proceedings of the 20th Annual International Symposium on Computer Architecture, pp. 289\u2013300 (May 1993)","DOI":"10.1145\/165123.165164"},{"key":"9_CR12","doi-asserted-by":"crossref","unstructured":"Scherer III, W.N., Scott, M.L.: Advanced contention management for dynamic software transactional memory. In: 24th ACM Symposium on Principles of Distributed Computing (July 2005)","DOI":"10.1145\/1073814.1073861"},{"key":"9_CR13","unstructured":"Scherer III, W.N., Scott, M.L.: Randomization in stm contention management. In: Proceedings of the 24th ACM Symposium on Principles of Distributed Computing (July 2005)"},{"key":"9_CR14","doi-asserted-by":"crossref","unstructured":"Martin, M.M., Sorin, D.J., Beckmann, B.M., Marty, M.R., Min Xu, A.R.A., Moore, K.E., Hill, M.D., Wood, D.A.: Multifacet\u2019s general execution-driven multiprocessor simulator toolset. In: Computer Architecture News, pp. 92\u201399 (September 2005)","DOI":"10.1145\/1105734.1105747"},{"key":"9_CR15","doi-asserted-by":"crossref","unstructured":"Moore, K.E., Bobba, J., Moravan, M.J., Hill, M.D., Wood, D.A.: Log-based transactional memory. In: Proceedings of the 12th IEEE Symposium on High-Performance Computer Architecture, pp. 258\u2013269 (February 2006)","DOI":"10.1109\/HPCA.2006.1598134"},{"key":"9_CR16","doi-asserted-by":"crossref","unstructured":"Rajwar, R., Goodman, J.R.: Transactional lock-free execution of lock-based programs. In: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (October 2002)","DOI":"10.1145\/605397.605399"},{"key":"9_CR17","doi-asserted-by":"crossref","unstructured":"Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The splash-2 programs: Characterization and methodological considerations. In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, pp. 24\u201337 (June 1995)","DOI":"10.1145\/223982.223990"},{"key":"9_CR18","doi-asserted-by":"crossref","unstructured":"Yen, L., Bobba, J., Marty, M.R., Moore, K.E., Volos, H., Hill, M.D., Swift, M.M., Wood, D.A.: Logtm-se: Decoupling hardware transactional memory from caches. In: Proceedings of the 13th IEEE Symposium on High-Performance Computer Architecture, pp. 261\u2013272 (February 2007)","DOI":"10.1109\/HPCA.2007.346204"}],"container-title":["Lecture Notes in Computer Science","Algorithms and Architectures for Parallel Processing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-24650-0_9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,13]],"date-time":"2025-03-13T05:50:28Z","timestamp":1741845028000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-24650-0_9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"ISBN":["9783642246494","9783642246500"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-24650-0_9","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2011]]}}}