{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:39:14Z","timestamp":1761647954190,"version":"3.40.2"},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642283642"},{"type":"electronic","value":"9783642283659"}],"license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-28365-9_13","type":"book-chapter","created":{"date-parts":[[2012,3,22]],"date-time":"2012-03-22T20:56:38Z","timestamp":1332449798000},"page":"151-162","source":"Crossref","is-referenced-by-count":5,"title":["Scalable Memory Hierarchies for Embedded Manycore Systems"],"prefix":"10.1007","author":[{"given":"Sen","family":"Ma","sequence":"first","affiliation":[]},{"given":"Miaoqing","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Eugene","family":"Cartwright","sequence":"additional","affiliation":[]},{"given":"David","family":"Andrews","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"13_CR1","unstructured":"Ge, Z., Lim, H.B., Wong, W.F.: A reconfigurable instruction memory hierarchy for embedded systems. In: Proc. 15th International Conference on Field Programmable Logic and Applications (FPL 2005), pp. 7\u201312 (August 2005)"},{"key":"13_CR2","doi-asserted-by":"crossref","unstructured":"Ge, Z., Wong, W.F., Lim, H.B.: DRIM: A low power dynamically reconfigurable instruction memory hierarchy for embedded systems. In: Proc. Conference on Design, Automation and Test in Europe (DATE 2007), pp. 1\u20136 (April 2007)","DOI":"10.1109\/DATE.2007.364484"},{"key":"13_CR3","doi-asserted-by":"crossref","unstructured":"Kandemir, M., Choudhary, A.: Compiler-directed scratch pad memory hierarchy design and management. In: Proc. 39th Annual Design Automation Conference (DAC 2002), pp. 628\u2013633 (June 2002)","DOI":"10.1145\/514074.514077"},{"key":"13_CR4","doi-asserted-by":"crossref","unstructured":"Kumar, A., Peh, L.S., Kundu, P., Jha, N.K.: Express virtual channels: towards the ideal interconnection fabric. In: Proc. 34th Annual International Symposium on Computer Architecture (ISCA 2007), pp. 150\u2013161 (June 2007)","DOI":"10.1145\/1250662.1250681"},{"issue":"3","key":"13_CR5","doi-asserted-by":"publisher","first-page":"682","DOI":"10.1145\/348019.348570","volume":"5","author":"P.R. Panda","year":"2000","unstructured":"Panda, P.R., Dutt, N.D., Nicolau, A.: On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Trans. Des. Autom. Electron. Syst.\u00a05(3), 682\u2013704 (2000)","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"13_CR6","doi-asserted-by":"crossref","unstructured":"Peck, W., Anderson, E., Agron, J., Stevens, J., Baijot, F., Andrews, D.: Hthreads: A computational model for reconfigurable devices. In: Proc. 16th International Conference on Field Programmable Logic and Applications (FPL 2006), pp. 885\u2013888 (August 2006)","DOI":"10.1109\/FPL.2006.311336"},{"key":"13_CR7","unstructured":"Steinke, S., Wehmeyer, L., Lee, B.S., Marwedel, P.: Assigning program and data objects to scratchpad for energy reduction. In: Proc. Conference on Design, Automation and Test in Europe (DATE 2002), pp. 409\u2013415 (March 2002)"},{"key":"13_CR8","doi-asserted-by":"crossref","unstructured":"Thoziyoor, S., Ahn, J.H., Monchiero, M., Brockman, J.B., Jouppi, N.P.: A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies. In: Proc. 35th Annual International Symposium on Computer Architecture (ISCA 2008), pp. 51\u201362 (June 2008)","DOI":"10.1109\/ISCA.2008.16"},{"key":"13_CR9","doi-asserted-by":"crossref","unstructured":"Verma, M., Wehmeyer, L., Marwedel, P.: Cache-aware scratchpad allocation algorithm. In: Proc. Conference on Design, automation and test in Europe (DATE 2004), pp. 1264\u20131269 (February 2004)","DOI":"10.1109\/DATE.2004.1269069"},{"key":"13_CR10","doi-asserted-by":"crossref","unstructured":"Yan, S., Zhou, X., Gao, Y., Chen, H., Luo, S., Zhang, P., Cherukuri, N., Ronen, R., Saha, B.: Terascale chip multiprocessor memory hierarchy and programming model. In: Proc. 2009 International Conference on High Performance Computing (HiPC 2009), pp. 150\u2013159 (December 2009)","DOI":"10.1109\/HIPC.2009.5433215"}],"container-title":["Lecture Notes in Computer Science","Reconfigurable Computing: Architectures, Tools and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-28365-9_13","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,23]],"date-time":"2025-03-23T18:53:01Z","timestamp":1742755981000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-28365-9_13"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642283642","9783642283659"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-28365-9_13","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]}}}