{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T00:49:46Z","timestamp":1725670186838},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642283642"},{"type":"electronic","value":"9783642283659"}],"license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-28365-9_28","type":"book-chapter","created":{"date-parts":[[2012,3,22]],"date-time":"2012-03-22T16:56:38Z","timestamp":1332435398000},"page":"329-334","source":"Crossref","is-referenced-by-count":0,"title":["Reconfigurable Multicore Architecture for Dynamic Processor Reallocation"],"prefix":"10.1007","author":[{"given":"Annie","family":"Avakian","sequence":"first","affiliation":[]},{"given":"Natwar","family":"Agrawal","sequence":"additional","affiliation":[]},{"given":"Ranga","family":"Vemuri","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"28_CR1","volume-title":"Interconnection Networks: An Engineering Approach","author":"J. Duato","year":"2002","unstructured":"Duato, J., Yalamanchili, S., Lionel, N.: Interconnection Networks: An Engineering Approach. Morgan Kaufmann Publishers Inc., San Francisco (2002)"},{"key":"28_CR2","doi-asserted-by":"crossref","unstructured":"Foglia, P., Panicucci, F., Prete, C.A., Solinas, M.: Analysis of performance dependencies in nuca-based cmp systems. In: Symposium on Computer Architecture and High Performance Computing, pp. 49\u201356 (2009)","DOI":"10.1109\/SBAC-PAD.2009.12"},{"key":"28_CR3","doi-asserted-by":"publisher","first-page":"2","DOI":"10.1109\/HPCA.2007.346180","volume-title":"HPCA 2007: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture","author":"H. Dybdahl","year":"2007","unstructured":"Dybdahl, H., Stenstrom, P.: An adaptive shared\/private nuca cache partitioning scheme for chip multiprocessors. In: HPCA 2007: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, pp. 2\u201312. IEEE Computer Society, Washington, DC, USA (2007)"},{"key":"28_CR4","doi-asserted-by":"crossref","unstructured":"Das, R., Eachempati, S., Mishra, A.K., Narayanan, V., Das, C.R.: Design and evaluation of a hierarchical on-chip interconnect for next-generation cmps, pp. 175\u2013186 (February 2009)","DOI":"10.1109\/HPCA.2009.4798252"},{"key":"28_CR5","doi-asserted-by":"crossref","unstructured":"Avakian, A., Nafziger, J., Panda, A., Vemuri, R.: A reconfigurable architecture for multicore systems. In: 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), pp. 1\u20138. IEEE (2010)","DOI":"10.1109\/IPDPSW.2010.5470753"},{"key":"28_CR6","unstructured":"http:\/\/www.itrs.net\/"},{"key":"28_CR7","unstructured":"http:\/\/ark.intel.com\/Product.aspx?id=37150"},{"key":"28_CR8","unstructured":"http:\/\/www.virtutech.com"},{"key":"28_CR9","doi-asserted-by":"crossref","first-page":"72","DOI":"10.1145\/1454115.1454128","volume-title":"PACT 2008: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques","author":"C. Bienia","year":"2008","unstructured":"Bienia, C., Kumar, S., Singh, J.P., Li, K.: The parsec benchmark suite: characterization and architectural implications. In: PACT 2008: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, pp. 72\u201381. ACM, New York (2008)"},{"issue":"2","key":"28_CR10","doi-asserted-by":"publisher","first-page":"130","DOI":"10.1145\/1150019.1136497","volume":"34","author":"F. Li","year":"2006","unstructured":"Li, F., Nicopoulos, C., Richardson, T., Xie, Y., Narayanan, V., Kandemir, M.: Design and management of 3d chip multiprocessors using network-in-memory. SIGARCH Comput. Archit. News\u00a034(2), 130\u2013141 (2006)","journal-title":"SIGARCH Comput. Archit. News"}],"container-title":["Lecture Notes in Computer Science","Reconfigurable Computing: Architectures, Tools and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-28365-9_28","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,5]],"date-time":"2022-01-05T21:09:15Z","timestamp":1641416955000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-28365-9_28"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642283642","9783642283659"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-28365-9_28","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]}}}