{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,24]],"date-time":"2025-03-24T04:13:49Z","timestamp":1742789629253,"version":"3.40.2"},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642283642"},{"type":"electronic","value":"9783642283659"}],"license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-28365-9_31","type":"book-chapter","created":{"date-parts":[[2012,3,22]],"date-time":"2012-03-22T20:56:38Z","timestamp":1332449798000},"page":"350-356","source":"Crossref","is-referenced-by-count":3,"title":["PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs"],"prefix":"10.1007","author":[{"given":"Ruining","family":"He","sequence":"first","affiliation":[]},{"given":"Guoqiang","family":"Liang","sequence":"additional","affiliation":[]},{"given":"Yuchun","family":"Ma","sequence":"additional","affiliation":[]},{"given":"Yu","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Jinian","family":"Bian","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"31_CR1","unstructured":"Xilinx: Partial Reconfiguration User Guide (March 1, 2011)"},{"key":"31_CR2","doi-asserted-by":"crossref","unstructured":"Bazargan, K., Kastner, R., et al.: Fast Template Placement for Reconfigurable Computing Systems. Presented at IEEE Design & Test of Computers, pp. 68\u201383 (2000)","DOI":"10.1109\/54.825678"},{"key":"31_CR3","unstructured":"Ahmadinia, A., Teich, J.: Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead. In: Proc. VLSI-SOC, pp. 118\u2013122 (2003)"},{"key":"31_CR4","unstructured":"Walder, H., Steiger, C., et al.: Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing. In: Proc. IPDPS (2003)"},{"key":"31_CR5","doi-asserted-by":"crossref","unstructured":"Ahmadinia, A., Bobda, C., et al.: A New Approach for On-line Placement on Reconfigurable Devices. In: Proc. IPDPS, pp. 134\u2013140 (2004)","DOI":"10.1109\/IPDPS.2004.1303104"},{"key":"31_CR6","unstructured":"Cheng, L., Wong, M.D.F.: Floorplan Design for Multi-Million Gate FPGAs. In: ICCAD, pp. 292\u2013299 (2004)"},{"key":"31_CR7","doi-asserted-by":"crossref","unstructured":"Papadimitriou, K., Dollas, A., et al.: Performance of Partial Reconfiguration in FPGA Systems: A Survey and a Cost Model. ACM Transactions on Reconfigurable Technology and Systems 4(4) (2011)","DOI":"10.1145\/2068716.2068722"},{"key":"31_CR8","unstructured":"Yousuf, S., Gordon-Ross, A.: DAPR: Design Automation for Partially Reconfigurable FPGAs. In: Proc. ERSA, pp. 97\u2013103 (2010)"},{"key":"31_CR9","doi-asserted-by":"crossref","unstructured":"Singhal, L., Bozorgzadeh, E.: Multi-layer Floorplanning on a Sequence of Reconfigurable Designs. In: FPL, pp. 1\u20138 (2006)","DOI":"10.1109\/FPL.2006.311273"},{"key":"31_CR10","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"213","DOI":"10.1007\/3-540-63465-7_226","volume-title":"Field Programmable Logic and Applications","author":"V. Betz","year":"1997","unstructured":"Betz, V., Rose, J.: VPR: A New Packing, Placement and Routing Tool for FPGA Research. In: Glesner, M., Luk, W. (eds.) FPL 1997. LNCS, vol.\u00a01304, pp. 213\u2013222. Springer, Heidelberg (1997)"},{"key":"31_CR11","doi-asserted-by":"crossref","unstructured":"Sankar, Y., Rose, J.: Trading quality for compile time: Ultra-fast placement for FPGAs. In: FPGA, pp. 157\u2013166 (1999)","DOI":"10.1145\/296399.296449"},{"key":"31_CR12","doi-asserted-by":"crossref","unstructured":"Bian, H., Ling, A.C., et al.: Towards scalable placement for FPGAs. In: Proc. FPGA, pp. 147\u2013156 (2010)","DOI":"10.1145\/1723112.1723140"},{"key":"31_CR13","doi-asserted-by":"crossref","unstructured":"Luu, J., Kuon, I., et al.: VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. In: FPGA, pp. 133\u2013142 (2009)","DOI":"10.1145\/1508128.1508150"},{"key":"31_CR14","doi-asserted-by":"crossref","unstructured":"Banerjee, P., Sangtani, M., et al.: Floorplanning for Partially Reconfigurable FPGAs. Presented at IEEE Trans. on CAD of Integrated Circuits and Systems, pp. 8\u201317 (2011)","DOI":"10.1109\/TCAD.2010.2079390"}],"container-title":["Lecture Notes in Computer Science","Reconfigurable Computing: Architectures, Tools and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-28365-9_31","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,23]],"date-time":"2025-03-23T18:53:09Z","timestamp":1742755989000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-28365-9_31"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642283642","9783642283659"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-28365-9_31","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]}}}