{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,5]],"date-time":"2025-04-05T17:40:06Z","timestamp":1743874806646,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":88,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642289767"},{"type":"electronic","value":"9783642289774"}],"license":[{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-3-642-28977-4_2","type":"book-chapter","created":{"date-parts":[[2012,7,28]],"date-time":"2012-07-28T06:51:22Z","timestamp":1343458282000},"page":"23-81","source":"Crossref","is-referenced-by-count":0,"title":["Formal Methods in High-Level and System Synthesis"],"prefix":"10.1007","author":[{"given":"Michael F.","family":"Dossis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"6","key":"2_CR1","doi-asserted-by":"publisher","first-page":"1098","DOI":"10.1109\/TCAD.1987.1270350","volume":"6","author":"B.M. Pangrle","year":"1987","unstructured":"Pangrle, B.M., Gajski, D.D.: Design tools for intelligent silicon compilation. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst.\u00a06(6), 1098\u20131112 (1987)","journal-title":"IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst."},{"issue":"2","key":"2_CR2","doi-asserted-by":"publisher","first-page":"134","DOI":"10.1109\/TCAD.1985.1270106","volume":"4","author":"E.F. Girczyc","year":"1985","unstructured":"Girczyc, E.F., Buhr, R.J.A., Knight, J.P.: Applicability of a subset of Ada as an algorithmic hardware description language for graph-based hardware compilation. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst.\u00a04(2), 134\u2013142 (1985)","journal-title":"IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst."},{"issue":"6","key":"2_CR3","doi-asserted-by":"publisher","first-page":"661","DOI":"10.1109\/43.31522","volume":"8","author":"P.G. Paulin","year":"1989","unstructured":"Paulin, P.G., Knight, J.P.: Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst.\u00a08(6), 661\u2013679 (1989)","journal-title":"IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst."},{"key":"2_CR4","doi-asserted-by":"crossref","unstructured":"Park, I.C., Kyung, C.M.: Fast and near optimal scheduling in automatic data path synthesis. In: Proc. of the Des. Autom. Conf. (DAC), San Francisco, pp. 680\u2013685 (1991)","DOI":"10.1145\/127601.127750"},{"issue":"3","key":"2_CR5","doi-asserted-by":"publisher","first-page":"356","DOI":"10.1109\/43.3169","volume":"7","author":"N. Park","year":"1988","unstructured":"Park, N., Parker, A.: Sehwa: A software package for synthesis of pipelined data path from behavioral specification. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst.\u00a07(3), 356\u2013370 (1988)","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circuits Syst."},{"key":"2_CR6","unstructured":"Girczyc, E.F.: Loop winding\u2014a data flow approach to functional pipelining. In: Proc. of the International Symp. on Circ. and Syst., pp. 382\u2013385 (1987)"},{"issue":"3","key":"2_CR7","doi-asserted-by":"publisher","first-page":"379","DOI":"10.1109\/TCAD.1986.1270207","volume":"5","author":"C.J. Tseng","year":"1986","unstructured":"Tseng, C.J., Siewiorek, D.P.: Automatic synthesis of data path on digital systems. IEEE Trans. Comput. Aided Des. Integ. Circuits Syst.\u00a05(3), 379\u2013395 (1986)","journal-title":"IEEE Trans. Comput. Aided Des. Integ. Circuits Syst."},{"key":"2_CR8","doi-asserted-by":"crossref","unstructured":"Kurdahi, F.J., Parker, A.C.: REAL: A program for register allocation. In: Proc. of the Des. Autom. Conf. (DAC), Miami Beach, FL, pp. 210\u2013215 (June 1987)","DOI":"10.1145\/37888.37920"},{"key":"2_CR9","doi-asserted-by":"crossref","unstructured":"Huang, C.Y., Chen, Y.S., Lin, Y.L., Hsu, Y.C.: Data path allocation based on bipartite weighted matching. In: Proc. of the Des. Autom. Conf. (DAC), Orlando, FL, pp. 499\u2013504 (June 1990)","DOI":"10.1145\/123186.123350"},{"key":"2_CR10","unstructured":"Tsay, F.S., Hsu, Y.C.: Data path construction and refinement. In: Digest of Techn papers, Int. Conf. on Comp.-Aided Des. (ICCAD), Santa Clara, CA, pp. 308\u2013311 (November 1990)"},{"issue":"2","key":"2_CR11","doi-asserted-by":"publisher","first-page":"171","DOI":"10.1109\/43.21835","volume":"8","author":"R. Camposano","year":"1989","unstructured":"Camposano, R., Rosenstiel, W.: Synthesizing circuits from behavioral descriptions. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.\u00a08(2), 171\u2013180 (1989)","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"2_CR12","volume-title":"Synthesis of Digital Designs from Recursion Equations","author":"S.D. Johnson","year":"1984","unstructured":"Johnson, S.D.: Synthesis of Digital Designs from Recursion Equations. MIT Press, Cambridge (1984)"},{"key":"2_CR13","unstructured":"Barbacci, M.R., Barnes, G.E., Cattell, R.G., Siewiorek, D.P.: The ISPS Computer Description Language. Rep. CMU-CS-79-137, dep. of Computer Science, Carnegie-Mellon Univ. (1979)"},{"key":"2_CR14","doi-asserted-by":"crossref","unstructured":"Marwedel, P.: The MIMOLA design system: Tools for the design of digital processors. In: Proc. of the 21st Design Automation Conf., pp. 587\u2013593 (1984)","DOI":"10.1109\/DAC.1984.1585857"},{"issue":"2","key":"2_CR15","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1109\/54.19133","volume":"6","author":"A.E. Casavant","year":"1989","unstructured":"Casavant, A.E., d\u2019Abreu, M.A., Dragomirecky, M., Duff, D.A., Jasica, J.R., Hartman, M.J., Hwang, K.S., Smith, W.D.: A synthesis environment for designing DSP systems. IEEE Des. & Test of Comput.\u00a06(2), 35\u201344 (1989)","journal-title":"IEEE Des. & Test of Comput."},{"issue":"6","key":"2_CR16","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1109\/54.41671","volume":"6","author":"P.G. Paulin","year":"1989","unstructured":"Paulin, P.G., Knight, J.P.: Algorithms for high-level synthesis. IEEE Des. & Test of Comput.\u00a06(6), 18\u201331 (1989)","journal-title":"IEEE Des. & Test of Comput."},{"issue":"4","key":"2_CR17","doi-asserted-by":"publisher","first-page":"44","DOI":"10.1109\/54.329454","volume":"11","author":"D.D. Gajski","year":"1994","unstructured":"Gajski, D.D., Ramachandran, L.: Introduction to high-level synthesis. IEEE Des. & Test of Comput.\u00a011(4), 44\u201354 (1994)","journal-title":"IEEE Des. & Test of Comput."},{"issue":"2","key":"2_CR18","doi-asserted-by":"publisher","first-page":"60","DOI":"10.1109\/54.386007","volume":"12","author":"R.A. Walker","year":"1995","unstructured":"Walker, R.A., Chaudhuri, S.: Introduction to the scheduling problem. IEEE Des. & Test of Comput.\u00a012(2), 60\u201369 (1995)","journal-title":"IEEE Des. & Test of Comput."},{"issue":"2","key":"2_CR19","doi-asserted-by":"publisher","first-page":"8","DOI":"10.1109\/54.19131","volume":"6","author":"V. Berstis","year":"1989","unstructured":"Berstis, V.: The V compiler: automatic hardware design. IEEE Des. & Test of Comput.\u00a06(2), 8\u201317 (1989)","journal-title":"IEEE Des. & Test of Comput."},{"key":"2_CR20","volume-title":"Compiler Design in C","author":"A. Holub","year":"1990","unstructured":"Holub, A.: Compiler Design in C. Prentice-Hall Inc., Englewood Cliffs (1990)"},{"issue":"7","key":"2_CR21","doi-asserted-by":"publisher","first-page":"478","DOI":"10.1109\/TC.1981.1675827","volume":"C-30","author":"J. Fisher","year":"1981","unstructured":"Fisher, J.: Trace Scheduling: A technique for global microcode compaction. IEEE Trans. on Comput.\u00a0C-30(7), 478\u2013490 (1981)","journal-title":"IEEE Trans. on Comput."},{"key":"2_CR22","doi-asserted-by":"crossref","unstructured":"Kuehlmann, A., Bergamaschi, R.A.: Timing analysis in high-level synthesis. In: Proc. of the 1992 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD 1992), pp. 349\u2013354 (1992)","DOI":"10.1109\/ICCAD.1992.279348"},{"issue":"1","key":"2_CR23","doi-asserted-by":"publisher","first-page":"21","DOI":"10.1155\/1995\/23249","volume":"3","author":"T.C. Wilson","year":"1995","unstructured":"Wilson, T.C., Mukherjee, N., Garg, M.K., Banerji, D.K.: An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis. VLSI Design\u00a03(1), 21\u201336 (1995)","journal-title":"VLSI Design"},{"key":"2_CR24","doi-asserted-by":"crossref","unstructured":"Papachristou, C.A., Konuk, H.: A Linear program driven scheduling and allocation method followed by an interconnect optimization algorithm. In: Proc. of the 27th ACM\/IEEE Design Automation Conf., pp. 77\u201383 (1990)","DOI":"10.1145\/123186.123231"},{"issue":"3","key":"2_CR25","doi-asserted-by":"publisher","first-page":"244","DOI":"10.1109\/92.238438","volume":"1","author":"J. Biesenack","year":"1993","unstructured":"Biesenack, J., Koster, M., Langmaier, A., et al.: The Siemens high-level synthesis system CALLAS. IEEE Trans. on Very Large Scale Integr (VLSI) Sys.\u00a01(3), 244\u2013253 (1993)","journal-title":"IEEE Trans. on Very Large Scale Integr. (VLSI) Sys."},{"key":"2_CR26","unstructured":"The Electronic Design Interchange Format. Wikipedia, the free encyclopedia, http:\/\/en.wikipedia.org\/wiki\/EDIF (accessed February 4, 2011)"},{"key":"2_CR27","unstructured":"Rubin, M.S.: Computer Aids for VLSI Design. Appendix D: Electronic Design Interchange Format (1994), http:\/\/www.rulabinsky.com\/cavd\/text\/chapd.html (accessed February 4, 2011)"},{"key":"2_CR28","doi-asserted-by":"crossref","unstructured":"Filkorn, T.: A method for symbolic verification of synchronous circuits. In: Comp. Hardware Descr. Lang. and their Application (CHDL 1991), Marseille, France, pp. 229\u2013239 (1991)","DOI":"10.1016\/B978-0-444-89208-9.50020-X"},{"issue":"3","key":"2_CR29","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1109\/54.232469","volume":"10","author":"A. Kalavade","year":"1993","unstructured":"Kalavade, A., Lee, E.A.: A hardware-software codesign methodology for DSP applications. IEEE Des. & Test of Comput.\u00a010(3), 16\u201328 (1993)","journal-title":"IEEE Des. & Test of Comput."},{"issue":"4","key":"2_CR30","doi-asserted-by":"publisher","first-page":"64","DOI":"10.1109\/54.245964","volume":"10","author":"R. Ernst","year":"1993","unstructured":"Ernst, R., Henkel, J., Benner, T.: Hardware-software cosynthesis for microcontrollers. IEEE Des. & Test of Comput.\u00a010(4), 64\u201375 (1993)","journal-title":"IEEE Des. & Test of Comput."},{"issue":"5","key":"2_CR31","doi-asserted-by":"publisher","first-page":"37","DOI":"10.1109\/54.60605","volume":"7","author":"G. De Micheli","year":"1990","unstructured":"De Micheli, G., et al.: The Olympus synthesis system. IEEE Des. & Test of Comput.\u00a07(5), 37\u201353 (1990)","journal-title":"IEEE Des. & Test of Comput."},{"issue":"3","key":"2_CR32","doi-asserted-by":"publisher","first-page":"6","DOI":"10.1109\/54.232468","volume":"10","author":"D.E. Thomas","year":"1993","unstructured":"Thomas, D.E., Adams, J.K., Schmit, H.: A model and methodology for hardware-software codesign. IEEE Des. & Test of Comput.\u00a010(3), 6\u201315 (1993)","journal-title":"IEEE Des. & Test of Comput."},{"key":"2_CR33","volume-title":"Communicating sequential processes","author":"C.A.R. Hoare","year":"1985","unstructured":"Hoare, C.A.R.: Communicating sequential processes. Prentice-Hall, Englewood Cliffs (1985)"},{"issue":"3","key":"2_CR34","doi-asserted-by":"publisher","first-page":"29","DOI":"10.1109\/54.232470","volume":"10","author":"R.K. Gupta","year":"1993","unstructured":"Gupta, R.K., De Micheli, G.: Hardware-software cosynthesis for digital systems. IEEE Des. & Test of Comput.\u00a010(3), 29\u201341 (1993)","journal-title":"IEEE Des. & Test of Comput."},{"issue":"3","key":"2_CR35","doi-asserted-by":"publisher","first-page":"391","DOI":"10.1109\/5.558713","volume":"85","author":"I. Bolsens","year":"1997","unstructured":"Bolsens, I., De Man, H.J., Lin, B., Van Rompaey, K., Vercauteren, S., Verkest, D.: Hardware\/software co-design of digital telecommunication systems. Proc. of the IEEE\u00a085(3), 391\u2013418 (1997)","journal-title":"Proc. of the IEEE"},{"key":"2_CR36","unstructured":"Hilfinger, P.N., Rabaey, J., Genin, D., Scheers, C., De Man, H.: DSP specification using the SILAGE language. In: Proc. Int. Conf. on Acoust Speech Signal Process. Albuquerque, NM, pp. 1057\u20131060 (1990)"},{"issue":"1","key":"2_CR37","first-page":"8","volume":"3","author":"P. Willekens","year":"1994","unstructured":"Willekens, P., et al.: Algorithm specification in DSP station using data flow language. DSP Applicat.\u00a03(1), 8\u201316 (1994)","journal-title":"DSP Applicat."},{"key":"2_CR38","doi-asserted-by":"crossref","unstructured":"Halbwachs, N., Caspi, P., Raymond, P., Pilaud, D.: The synchronous dataflow programming language Lustre. Proc. IEEE\u00a079(9), 1305\u20131320","DOI":"10.1109\/5.97300"},{"issue":"5","key":"2_CR39","first-page":"6","volume":"3","author":"M. Van Canneyt","year":"1994","unstructured":"Van Canneyt, M.: Specification, simulation and implementation of a GSM speech codec with DSP station. DSP and Multimedia Technol.\u00a03(5), 6\u201315 (1994)","journal-title":"DSP and Multimedia Technol."},{"key":"2_CR40","unstructured":"Buck, J.T., et al.: PTOLEMY: A framework for simulating and prototyping heterogeneous systems. Int. J. Computer Simulation, 1\u201334 (August 31, 1992\/1994)"},{"issue":"2","key":"2_CR41","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1109\/2.347998","volume":"28","author":"R. Lauwereins","year":"1995","unstructured":"Lauwereins, R., et al.: GRAPE-II: A system level prototyping environment for DSP applications. IEEE Computer\u00a028(2), 35\u201343 (1995)","journal-title":"IEEE Computer"},{"issue":"6","key":"2_CR42","first-page":"6","volume":"3","author":"M.S. Rafie","year":"1994","unstructured":"Rafie, M.S., et al.: Rapid design and prototyping of a direct sequence spread-spectrum ASIC over a wireless link. DSP and Multimedia Technol.\u00a03(6), 6\u201312 (1994)","journal-title":"DSP and Multimedia Technol."},{"issue":"6","key":"2_CR43","doi-asserted-by":"publisher","first-page":"743","DOI":"10.1109\/92.974889","volume":"9","author":"L. Semeria","year":"2001","unstructured":"Semeria, L., Sato, K., De Micheli, G.: Synthesis of hardware models in C with pointers and complex data structures. IEEE Trans. VLSI Systems\u00a09(6), 743\u2013756 (2001)","journal-title":"IEEE Trans. VLSI Systems"},{"issue":"9","key":"2_CR44","first-page":"67","volume":"28","author":"R.P. Wilson","year":"1994","unstructured":"Wilson, R.P., et al.: Suif: An infrastructure for research on parallelizing and optimizing compilers. ACM SIPLAN Notices\u00a028(9), 67\u201370 (1994)","journal-title":"ACM SIPLAN Notices"},{"issue":"3","key":"2_CR45","doi-asserted-by":"publisher","first-page":"380","DOI":"10.1145\/567270.567272","volume":"7","author":"A. Kountouris","year":"2002","unstructured":"Kountouris, A., Wolinski, C.: Efficient Scheduling of Conditional Behaviors for High-Level Synthesis. ACM Trans. on Design Aut. of Electr. Sys.\u00a07(3), 380\u2013412 (2002)","journal-title":"ACM Trans. on Design Aut. of Electr. Sys."},{"issue":"4","key":"2_CR46","doi-asserted-by":"publisher","first-page":"441","DOI":"10.1145\/1027084.1027087","volume":"9","author":"S. Gupta","year":"2004","unstructured":"Gupta, S., Gupta, R.K., Dutt, N.D., Nikolau, A.: Coordinated Parallelizing Compiler Optimizations and High-Level Synthesis. ACM Trans. on Des. Aut. of Electr. Sys.\u00a09(4), 441\u2013470 (2004)","journal-title":"ACM Trans. on Des. Aut. of Electr. Sys."},{"key":"2_CR47","doi-asserted-by":"crossref","unstructured":"Wang, W., Tan, T.K., et al.: A comprehensive high-level synthesis system for control-flow intensive behaviors. In: Proc. 13th ACM Great Lakes Symp. on VLSI GLSVLSI 2003, pp. 11\u201314 (2003)","DOI":"10.1145\/764808.764812"},{"key":"2_CR48","doi-asserted-by":"crossref","unstructured":"Gu, Z.P., Wang, J., Dick, R.P., Zhou, H.: Incremental exploration of the combined physical and behavioral design space. In: Proc. of the 42nd Annual Conf. on Des. Aut. DAC 2005, pp. 208\u2013213 (2005)","DOI":"10.1145\/1065579.1065635"},{"key":"2_CR49","doi-asserted-by":"crossref","unstructured":"Zhong, L., Jha, N.K.: Interconnect-aware high-level synthesis for low power. In: Proc. IEEE\/ACM Int. Conf. Comp.-Aided Des., pp. 110\u2013117 (November 2002)","DOI":"10.1145\/774572.774588"},{"issue":"11","key":"2_CR50","doi-asserted-by":"publisher","first-page":"1191","DOI":"10.1109\/TVLSI.2007.904096","volume":"15","author":"C. Huang","year":"2007","unstructured":"Huang, C., Ravi, S., Raghunathan, A., Jha, N.K.: Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. IEEE Trans. on Very Large Scale Integr (VLSI) Sys.\u00a015(11), 1191\u20131204 (2007)","journal-title":"IEEE Trans. on Very Large Scale Integr. (VLSI) Sys."},{"key":"2_CR51","doi-asserted-by":"crossref","unstructured":"Wakabayashi, K.: C-based synthesis experiences with a behavior synthesizer, \u201cCyber\u201d. In: Proc. Des. Autom. and Test in Eur. Conf., pp. 390\u2013393 (1999)","DOI":"10.1145\/307418.307530"},{"key":"2_CR52","unstructured":"Wang, W., Raghunathan, A., Jha, N.K., Dey, S.: High-level Synthesis of Multi-process Behavioral Descriptions. In: Proc. of the 16th IEEE International Conference on VLSI Design (VLSI 2003), pp. 467\u2013473 (2003)"},{"issue":"11","key":"2_CR53","first-page":"1454","volume":"16","author":"B.L. Gal","year":"2008","unstructured":"Gal, B.L., Casseau, E., Huet, S.: Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst.\u00a016(11), 1454\u20131464 (2008)","journal-title":"IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst."},{"key":"2_CR54","doi-asserted-by":"crossref","unstructured":"Wakabayashi, K., Tanaka, H.: Global scheduling independent of control dependencies based on condition vectors. In: Proc. 29th ACM\/IEEE Conf. Des. Autom (DAC), Los Alamitos, CA, pp. 112\u2013115 (1992)","DOI":"10.1109\/DAC.1992.227852"},{"key":"2_CR55","doi-asserted-by":"crossref","unstructured":"Gupta, S., Gupta, R., Dutt, N., Nicolau, A.: Dynamically increasing the scope of code motions during the high-level synthesis of digital circuits. In: Proc. IEEE Conf. Comput. Digit. Techn., vol.\u00a0150(5), pp. 330\u2013337 (2003)","DOI":"10.1049\/ip-cdt:20030839"},{"key":"2_CR56","doi-asserted-by":"crossref","unstructured":"Martin, E., Santieys, O., Philippe, J.: GAUT, an architecture synthesis tool for dedicated signal processors. In: Proc. IEEE Int. Eur. Des. Autom. Conf. (Euro-DAC), Hamburg, Germany, pp. 14\u201319 (1993)","DOI":"10.1109\/EURDAC.1993.410610"},{"issue":"1","key":"2_CR57","doi-asserted-by":"publisher","first-page":"60","DOI":"10.1109\/TCAD.2008.2009140","volume":"28","author":"M.C. Molina","year":"2009","unstructured":"Molina, M.C., Ruiz-Sautua, R., Garcia-Repetto, P., Hermida, R.: Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst.\u00a028(1), 60\u201373 (2009)","journal-title":"IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst."},{"issue":"2","key":"2_CR58","first-page":"19","volume":"14","author":"K. Avnit","year":"2009","unstructured":"Avnit, K., D\u2019silva, V., Sowmya, A., Ramesh, S., Parameswaran, S.: Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis. ACM Trans. on Des. Autom. of Electr. Sys (TODAES)\u00a014(2), article no: 19 (2009)","journal-title":"ACM Trans. on Des. Autom. of Electr. Sys (TODAES)"},{"key":"2_CR59","doi-asserted-by":"crossref","unstructured":"Keinert, J., Streubuhr, M., Schlichter, T., Falk, J., Gladigau, J., Haubelt, C., Teich, J., Meredith, M.: System Co Designer\u2014an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications. ACM Trans. on Des. Autom. of Electr. Sys. (TODAES)\u00a014(1), article no: 1 (2009)","DOI":"10.1145\/1455229.1455230"},{"issue":"4","key":"2_CR60","doi-asserted-by":"publisher","first-page":"566","DOI":"10.1109\/TCAD.2010.2042889","volume":"29","author":"S. Kundu","year":"2010","unstructured":"Kundu, S., Lerner, S., Gupta, R.K.: Translation Validation of High-Level Synthesis. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst.\u00a029(4), 566\u2013579 (2010)","journal-title":"IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst."},{"key":"2_CR61","unstructured":"Falk, J., Haubelt, C., Teich, J.: Efficient representation and simulation of model-based designs in SystemC. In: Proc. of the Forum of Des. Lang., Darmstadt, Germany, September 19-22, pp. 129\u2013134 (2006)"},{"issue":"5","key":"2_CR62","doi-asserted-by":"publisher","first-page":"657","DOI":"10.1109\/TCAD.2010.2043588","volume":"29","author":"S. Paik","year":"2010","unstructured":"Paik, S., Shin, I., Kim, T., Shin, Y.: HLS-l: A High-Level Synthesis framework for latch-based architectures. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst.\u00a029(5), 657\u2013670 (2010)","journal-title":"IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst."},{"key":"2_CR63","doi-asserted-by":"crossref","unstructured":"Voros, N., Rosti, A., Hubner, M. (eds.): Dynamic System Reconfiguration in Heterogeneous Platforms: The MORPHEUS Approach. LNEE, vol.\u00a040. Springer Science+Business Media B.V (2009)","DOI":"10.1007\/978-90-481-2427-5"},{"issue":"4","key":"2_CR64","doi-asserted-by":"publisher","first-page":"451","DOI":"10.1109\/43.275355","volume":"13","author":"M. Rim","year":"1994","unstructured":"Rim, M., Jain, R.: Lower-bound performance estimation for the high level synthesis scheduling problem. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst.\u00a013(4), 451\u2013458 (1994)","journal-title":"IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst."},{"issue":"2","key":"2_CR65","doi-asserted-by":"publisher","first-page":"273","DOI":"10.1109\/92.502199","volume":"4","author":"S. Chaudhuri","year":"1996","unstructured":"Chaudhuri, S., Walker, R.A.: Computing lower bounds on functional units before scheduling. IEEE Trans. Very Large Scale Integ (VLSI) Syst.\u00a04(2), 273\u2013279 (1996)","journal-title":"IEEE Trans. Very Large Scale Integ (VLSI) Syst."},{"issue":"2","key":"2_CR66","doi-asserted-by":"publisher","first-page":"258","DOI":"10.1109\/43.486671","volume":"15","author":"H. Mecha","year":"1996","unstructured":"Mecha, H., Fernandez, M., et al.: A method for area estimation of data path in high level synthesis. IEEE Trans. Comput. Aided Des. Integ. Circuits Syst.\u00a015(2), 258\u2013265 (1996)","journal-title":"IEEE Trans. Comput. Aided Des. Integ. Circuits Syst."},{"key":"2_CR67","unstructured":"Fang, Y.M., Wong, D.F.: Simultaneous functional-unit binding and floorplanning. Digest of Technical Papers. In: Intern. Conf. on Comp.-Aided Des (ICCAD), Santa Clara, CA, pp. 317\u2013321 (1994)"},{"key":"2_CR68","doi-asserted-by":"crossref","unstructured":"Munch, M., Wehn, N., Glesner, M.: Optimum simultaneous placement and binding for bit-slice architectures. In: Proc. of the Asia and South-Pacific Des. Autom. Conf (ASP-DAC), Chiba, Japan, pp. 735\u2013740 (1995)","DOI":"10.1109\/ASPDAC.1995.486396"},{"key":"2_CR69","doi-asserted-by":"crossref","unstructured":"Ahmadi, A., Zwolinski, M.: Multiple-Width Bus Partitioning Approach to Datapath Synthesis. In: IEEE International Symposium on Circuits and Systems (ISCAS 2007), pp. 2994\u20132997 (2007)","DOI":"10.1109\/ISCAS.2007.377976"},{"issue":"1-2","key":"2_CR70","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1007\/BF00993312","volume":"7","author":"R. Gupta","year":"1995","unstructured":"Gupta, R., Breuer, M.A.: Partial scan design of register-transfer level circuits. Journal of Electr. Test Theory and Appl.\u00a07(1-2), 25\u201346 (1995)","journal-title":"Journal of Electr. Test Theory and Appl."},{"key":"2_CR71","doi-asserted-by":"crossref","unstructured":"Flottes, M.L., Hammad, D., Rouzeyre, B.: High level synthesis for easy testability. In: Proc. European Des. and Test Conf., Paris, France, pp. 198\u2013206 (1995)","DOI":"10.1109\/EDTC.1995.470392"},{"issue":"8","key":"2_CR72","doi-asserted-by":"publisher","first-page":"934","DOI":"10.1109\/43.402494","volume":"14","author":"M.K. Dhodhi","year":"1995","unstructured":"Dhodhi, M.K., Hielscher, F.H., Storer, R.H., Bhasker, J.: Datapath synthesis using a problem-space genetic algorithm. IEEE Trans. Comput-Aided Des. Integ. Circuits and Syst.\u00a014(8), 934\u2013944 (1995)","journal-title":"IEEE Trans. Comput-Aided Des. Integ. Circuits and Syst."},{"issue":"1","key":"2_CR73","doi-asserted-by":"publisher","first-page":"43","DOI":"10.1007\/BF00971962","volume":"5","author":"A. Mujumdar","year":"1994","unstructured":"Mujumdar, A., Jain, R., Saluja, K.: Incorporating testability considerations in high level synthesis. Journal of Electr. Test Theory and Appl.\u00a05(1), 43\u201355 (1994)","journal-title":"Journal of Electr. Test Theory and Appl."},{"key":"2_CR74","doi-asserted-by":"crossref","unstructured":"Potkonjak, M., Dey, S., Roy, R.K.: Synthesis-for-testability using transformations. In: Proc. of the Asia and South-Pacific Des., pp. 485\u2013490 (1995)","DOI":"10.1145\/224818.224961"},{"key":"2_CR75","doi-asserted-by":"crossref","unstructured":"Hsu, F.F., Rudnick, E.M., Patel, J.H.: Enhancing high-level control-flow for improved testability. Dig. of Techn. Papers. In: Intern. Conf. on Comp.-Aided Des (ICCAD), San Jose, CA, pp. 322\u2013328 (November 1996)","DOI":"10.1109\/ICCAD.1996.569720"},{"key":"2_CR76","doi-asserted-by":"crossref","unstructured":"Raghunathan, A., Dey, S., Jha, N.K.: Register-transfer level estimation techniques for switching activity and power consumption. Dig. of Techn. Papers. In: Intern. Conf. on Comp-Aided Des (ICCAD), San Jose, CA, pp. 158\u2013165 (November 1996)","DOI":"10.1109\/ICCAD.1996.569539"},{"key":"2_CR77","doi-asserted-by":"crossref","unstructured":"Rabaey, J., Guerra, L., Mehra, R.: Design guidance in the power dimension. In: 1995 Intern. Conf. on Acoustics, Speech, and Signal Proc., pp. 2837\u20132840 (1995)","DOI":"10.1109\/ICASSP.1995.479435"},{"key":"2_CR78","doi-asserted-by":"crossref","unstructured":"Mehra, R., Rabaey, J.: Exploiting regularity for low-power design. Dig. of Techn. Papers. In: Intern. Conf. on Comp.-Aided Des (ICCAD), San Jose, CA, pp. 166\u2013172 (November 1996)","DOI":"10.1109\/ICCAD.1996.569540"},{"key":"2_CR79","doi-asserted-by":"crossref","unstructured":"Raghunathan, A., Jha, N.K.: Behavioral synthesis for low power. In: Proc. of the Intern. Conf. on Comp. Des (ICCD), pp. 318\u2013322 (1994)","DOI":"10.1109\/ICCD.1994.331915"},{"key":"2_CR80","doi-asserted-by":"crossref","unstructured":"Goodby, L., Orailoglu, A., Chau, P.M.: Microarchitecture synthesis of performance-constrained low-power VLSI designs. In: Proc. of the Intern. Conf. on Comp. Des. (ICCD), pp. 323\u2013326 (1994)","DOI":"10.1109\/ICCD.1994.331916"},{"key":"2_CR81","doi-asserted-by":"crossref","unstructured":"Musoll, E., Cortadella, J.: Scheduling and resource binding for low power. In: Proc. the Eighth Symp. on Sys. Synth., pp. 104\u2013109 (1995)","DOI":"10.1145\/224486.224523"},{"issue":"3","key":"2_CR82","doi-asserted-by":"publisher","first-page":"70","DOI":"10.1109\/MDT.1995.466383","volume":"12","author":"N. Kumar","year":"1995","unstructured":"Kumar, N., Katkoori, S., Rader, L., Vemuri, R.: Profile-driven behavioral synthesis for low-power VLSI systems. IEEE Des. Test Comput.\u00a012(3), 70\u201384 (1995)","journal-title":"IEEE Des. Test Comput."},{"key":"2_CR83","doi-asserted-by":"crossref","unstructured":"Martin, R.S., Knight, J.P.: Power-profiler: Optimizing ASICs power consumption at the behavioral level. In: Proc. of the Des. Autom. Conf (DAC), San Francisco, CA, pp. 42\u201347 (1995)","DOI":"10.1145\/217474.217504"},{"issue":"8","key":"2_CR84","doi-asserted-by":"publisher","first-page":"1439","DOI":"10.1109\/TCAD.2008.925781","volume":"27","author":"I. Issenin","year":"2008","unstructured":"Issenin, I., Brockmeyer, E., Durinck, B., Dutt, N.D.: Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications. IEEE Trans. on Comp.-Aided Des. of Integr. Circ. and Sys.\u00a027(8), 1439\u20131452 (2008)","journal-title":"IEEE Trans. on Comp.-Aided Des. of Integr. Circ. and Sys."},{"key":"2_CR85","unstructured":"Rao, D.S., Kurdahi, F.J.: Controller and datapath trade-offs in hierarchical RT-level synthesis. In: Proc. of the Int. Symp. on High Level Synth., pp. 152\u2013157 (1994)"},{"key":"2_CR86","doi-asserted-by":"crossref","unstructured":"Huang, S.C.Y., Wolf, W.H.: How datapath allocation affects controller delay. In: Proc. of the Intern. Symp. on High Level Synth., Niagra Falls, Canada, pp. 158\u2013163 (1994)","DOI":"10.1109\/ISHLS.1994.302326"},{"issue":"1","key":"2_CR87","doi-asserted-by":"publisher","first-page":"100","DOI":"10.4156\/jnit.vol1.issue1.9","volume":"1","author":"M. Dossis","year":"2010","unstructured":"Dossis, M.: Intermediate Predicate Format for design automation tools. Journal of Next Generation Information Technology (JNIT)\u00a01(1), 100\u2013117 (2010)","journal-title":"Journal of Next Generation Information Technology (JNIT)"},{"key":"2_CR88","unstructured":"Nilsson, U., Maluszynski, J.: Logic Programming and Prolog, 2nd edn. John Wiley & Sons Ltd. (1995)"}],"container-title":["Studies in Computational Intelligence","Semantic Hyper\/Multimedia Adaptation"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-28977-4_2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,5]],"date-time":"2025-04-05T17:02:13Z","timestamp":1743872533000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-642-28977-4_2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9783642289767","9783642289774"],"references-count":88,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-28977-4_2","relation":{},"ISSN":["1860-949X","1860-9503"],"issn-type":[{"type":"print","value":"1860-949X"},{"type":"electronic","value":"1860-9503"}],"subject":[],"published":{"date-parts":[[2013]]}}}