{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,24]],"date-time":"2025-03-24T21:10:04Z","timestamp":1742850604857,"version":"3.40.2"},"publisher-location":"Berlin, Heidelberg","reference-count":7,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642292798"},{"type":"electronic","value":"9783642292804"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-29280-4_53","type":"book-chapter","created":{"date-parts":[[2012,4,2]],"date-time":"2012-04-02T07:12:18Z","timestamp":1333350738000},"page":"451-460","source":"Crossref","is-referenced-by-count":0,"title":["Obstacle Aware Routing in 3D Integrated Circuits"],"prefix":"10.1007","author":[{"given":"Prasun","family":"Ghosal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hafizur","family":"Rahaman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satrajit","family":"Das","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arindam","family":"Das","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Parthasarathi","family":"Dasgupta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"53_CR1","doi-asserted-by":"crossref","unstructured":"Sapatnekar, S., Goplen, B.: Placement of 3D ICs with thermal and inter-layer via considerations. In: Design Automation Conference, pp. 626\u2013631 (June 2007)","DOI":"10.1109\/DAC.2007.375239"},{"key":"53_CR2","unstructured":"Kahng, A.B., Robins, G.: A New Class of Steiner Tree Heuristics with Good Performance: The Iterated 1-Steiner approach. In: International Conference on CAD (1990)"},{"volume-title":"Three-Dimensional Integrated Circuit Design Series: Integrated Circuits and Systems","year":"2009","key":"53_CR3","unstructured":"Xie, Y., Cong, J., Sapatnekar, S. (eds.): Three-Dimensional Integrated Circuit Design Series: Integrated Circuits and Systems. Springer, Heidelberg (2009)"},{"key":"53_CR4","unstructured":"http:\/\/www.vlsicad.eecs.umich.edu\/BK\/PDtools\/"},{"key":"53_CR5","doi-asserted-by":"crossref","unstructured":"Deng, Y., Maly, W.: Interconnect Characteristics of 2.5d system integration scheme. In: ACM International Symposium on Physical Design, pp. 171\u2013175 (April 2001)","DOI":"10.1145\/369691.369763"},{"key":"53_CR6","doi-asserted-by":"crossref","unstructured":"Shi, Y., Mesa, P., Yu, H., He, L.: Circuit-Simulated Obstacle-Aware Steiner Routing. ACM Transactions on Design Automation of Electronic Systems\u00a012(3), Article 28 (August 2007)","DOI":"10.1145\/1255456.1255465"},{"key":"53_CR7","unstructured":"Yan, J.-T., Jhong, M.-C., Chen, Z.-W.: Obstacle-Aware Longest Path using Rectangular Pattern Detouring in Routing Grids. In: Asia and South Pacific Design Automation Conference, ASPDAC (2010)"}],"container-title":["Lecture Notes in Computer Science","Advanced Computing, Networking and Security"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-29280-4_53.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,24]],"date-time":"2025-03-24T20:40:45Z","timestamp":1742848845000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-29280-4_53"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642292798","9783642292804"],"references-count":7,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-29280-4_53","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]}}}