{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,23]],"date-time":"2024-09-23T03:51:00Z","timestamp":1727063460819},"publisher-location":"Berlin, Heidelberg","reference-count":5,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642314933"},{"type":"electronic","value":"9783642314940"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-31494-0_25","type":"book-chapter","created":{"date-parts":[[2012,6,27]],"date-time":"2012-06-27T13:28:40Z","timestamp":1340803720000},"page":"217-222","source":"Crossref","is-referenced-by-count":5,"title":["Design of a Fault-Tolerant Conditional Sum Adder"],"prefix":"10.1007","author":[{"given":"Atin","family":"Mukherjee","sequence":"first","affiliation":[]},{"given":"Anindya Sundar","family":"Dhar","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"issue":"1\/2\/3","key":"25_CR1","doi-asserted-by":"publisher","first-page":"117","DOI":"10.1504\/IJCCBS.2010.031709","volume":"1","author":"J. Biernat","year":"2010","unstructured":"Biernat, J.: Fast fault-tolerant adders. International Journal Critical Computer-Based Systems\u00a01(1\/2\/3), 117\u2013127 (2010)","journal-title":"International Journal Critical Computer-Based Systems"},{"key":"25_CR2","unstructured":"Koren, I.: Computer Arithmetic Algorithms. A K Peters (2011)"},{"key":"25_CR3","doi-asserted-by":"publisher","first-page":"146","DOI":"10.1109\/92.365462","volume":"3","author":"S.K. Lu","year":"1995","unstructured":"Lu, S.K., Wang, J.C., Wu, C.W.: C-testable design techniques for iterative logic arrays. IEEE Trans. VLSI Systems\u00a03, 146\u2013152 (1995)","journal-title":"IEEE Trans. VLSI Systems"},{"key":"25_CR4","doi-asserted-by":"publisher","DOI":"10.1002\/0471457787","volume-title":"Digital logic testing and simulation","author":"A. Miczo","year":"2003","unstructured":"Miczo, A.: Digital logic testing and simulation. John Wiley & Sons, New Jersey (2003)"},{"key":"25_CR5","unstructured":"Li, J.F., Hsu, C.C.: Efficient testing methodologies for conditional sum adders. In: Proc. Asian Test Symp., pp. 319\u2013324 (2004)"}],"container-title":["Lecture Notes in Computer Science","Progress in VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-31494-0_25.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,4]],"date-time":"2021-05-04T12:03:56Z","timestamp":1620129836000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-31494-0_25"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642314933","9783642314940"],"references-count":5,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-31494-0_25","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]}}}