{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,3]],"date-time":"2025-04-03T04:20:45Z","timestamp":1743654045987,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642314933"},{"type":"electronic","value":"9783642314940"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-31494-0_32","type":"book-chapter","created":{"date-parts":[[2012,6,27]],"date-time":"2012-06-27T13:28:40Z","timestamp":1340803720000},"page":"281-288","source":"Crossref","is-referenced-by-count":0,"title":["On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits"],"prefix":"10.1007","author":[{"given":"Lafifa","family":"Jamal","sequence":"first","affiliation":[]},{"given":"Md. Masbaul Alam","family":"Polash","sequence":"additional","affiliation":[]},{"given":"M. A.","family":"Mottalib","sequence":"additional","affiliation":[]},{"given":"Hafiz Md. Hasan","family":"Babu","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"32_CR1","doi-asserted-by":"publisher","first-page":"183","DOI":"10.1147\/rd.53.0183","volume":"5","author":"R. Landauer","year":"1961","unstructured":"Landauer, R.: Irreversibility and Heat Generation in the Computing Process. IBM Journal of Research and Development\u00a05, 183\u2013191 (1961)","journal-title":"IBM Journal of Research and Development"},{"issue":"6","key":"32_CR2","doi-asserted-by":"publisher","first-page":"525","DOI":"10.1147\/rd.176.0525","volume":"17","author":"C.H. Bennett","year":"1973","unstructured":"Bennett, C.H.: Logical Reversibility of computation. IBM Journal of Research and Development\u00a017(6), 525\u2013532 (1973)","journal-title":"IBM Journal of Research and Development"},{"key":"32_CR3","unstructured":"Perkowski, M., Al-Rabadi, A., Kerntopf, P., Buller, A., Chrzanowskajeske, M., Mischenko, A., Khan, M.A., Coppola, A., Yanushkevich, S., Shmerko, V., Jozwiak, L.: A general decomposition for reversible logic. In: Reed-Muller Workshop, pp. 119\u2013138 (2001)"},{"key":"32_CR4","unstructured":"Perkowski, M., Kerntopf, P.: Reversible Logic. In: EURO-MICRO, Warsaw, Poland (2001) (invited tutorial)"},{"key":"32_CR5","doi-asserted-by":"crossref","unstructured":"Babu, H.M.H., Islam, M.R., Chowdhury, A.R., Chowdhury, S.M.A.: Reversible Logic Synthesis for minimization of full-adder circuit. In: Euromicro Symposium on Digital System Design, Belek, Antalya, Turkey, pp. 50\u201354 (2003)","DOI":"10.1109\/DSD.2003.1231899"},{"key":"32_CR6","doi-asserted-by":"crossref","unstructured":"Babu, H.M.H., Islam, M.R., Chowdhury, A.R., Chowdhury, S.M.A.: Synthesis of full-adder circuit using reversible logic. In: 17th IEEE International Conference on VLSI Design, pp. 757\u2013760 (2004)","DOI":"10.1109\/ICVD.2004.1261020"},{"issue":"5","key":"32_CR7","doi-asserted-by":"publisher","first-page":"272","DOI":"10.1016\/j.sysarc.2005.05.005","volume":"52","author":"H.M.H. Babu","year":"2006","unstructured":"Babu, H.M.H., Chowdhury, A.R.: Design of a compact reversible binary coded decimal adder circuit. Elsevier Journal of Systems Architecture\u00a052(5), 272\u2013282 (2006)","journal-title":"Elsevier Journal of Systems Architecture"},{"issue":"6","key":"32_CR8","doi-asserted-by":"publisher","first-page":"507","DOI":"10.1007\/BF01886518","volume":"16","author":"R.P. Feynman","year":"1986","unstructured":"Feynman, R.P.: Quantum mechanical computers. Foundations of Physics\u00a016(6), 507\u2013531 (1986)","journal-title":"Foundations of Physics"},{"key":"32_CR9","doi-asserted-by":"publisher","first-page":"219","DOI":"10.1007\/BF01857727","volume":"21","author":"E. Fredkin","year":"1982","unstructured":"Fredkin, E., Toffoli, T.: Conservative Logic. International Journal of Theoretical Physics\u00a021, 219\u2013253 (1982)","journal-title":"International Journal of Theoretical Physics"},{"key":"32_CR10","doi-asserted-by":"publisher","first-page":"282","DOI":"10.3844\/ajassp.2008.282.288","volume":"5","author":"M. Haghparast","year":"2008","unstructured":"Haghparast, M., Navi, K.: A Novel Reversible BCD Adder for Nanotechnology Based Systems. American Journal of Applied Sciences\u00a05, 282\u2013288 (2008)","journal-title":"American Journal of Applied Sciences"},{"key":"32_CR11","unstructured":"Perkowski, M.: A hierarchical approach to computer-aided design of quantum circuits. In: 6th International Symposium on Representations and Methodology of Future Computing Technology, pp. 201\u2013209 (2003)"},{"issue":"4","key":"32_CR12","doi-asserted-by":"publisher","first-page":"2855","DOI":"10.1103\/PhysRevA.53.2855","volume":"53","author":"J. Smolin","year":"1996","unstructured":"Smolin, J., Divivcenzo, D.P.: Five two-qubit gates are sufficient to implement the quantum fredkin gate. Physical Review\u00a053(4), 2855\u20132856 (1996)","journal-title":"Physical Review"},{"issue":"12","key":"32_CR13","doi-asserted-by":"crossref","first-page":"1693","DOI":"10.1016\/j.mejo.2008.04.003","volume":"39","author":"A.K. Biswas","year":"2008","unstructured":"Biswas, A.K., Hasan, M.M., Chowdhury, A.R., Babu, H.M.H.: Efficient Algorithms for Implementing Reversible Binary Coded Decimal Adders. Elsevier Journal of Microelectronics\u00a039(12), 1693\u20131703 (2008)","journal-title":"Elsevier Journal of Microelectronics"},{"key":"32_CR14","first-page":"31","volume":"2","author":"N. Huda","year":"2011","unstructured":"Huda, N., Anwar, S., Jamal, L., Babu, H.M.H.: Design of a Reversible Random Access Memory. Dhaka University Journal of Applied Science and Engineering\u00a02, 31\u201338 (2011)","journal-title":"Dhaka University Journal of Applied Science and Engineering"},{"key":"32_CR15","unstructured":"Sayem, A.S.M., Ueda, M.: Optimization of reversible sequential circuits. Journal of Computing\u00a02(6) (2010)"},{"key":"32_CR16","doi-asserted-by":"crossref","unstructured":"Thapliyal, H., Ranganathan, N.: Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. In: 23rd International Conference on VLSI Design, pp. 235\u2013240 (2010)","DOI":"10.1109\/VLSI.Design.2010.74"},{"key":"32_CR17","unstructured":"Thapliyal, H., Srinivas, M.B., Zwolinski, M.: A beginning in the reversible logic synthesis of sequential circuits. In: Proc. the Military and Aerospace Programmable Logic Devices Intl. Conf., Washington (2005)"}],"container-title":["Lecture Notes in Computer Science","Progress in VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-31494-0_32.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,2]],"date-time":"2025-04-02T18:45:31Z","timestamp":1743619531000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-31494-0_32"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642314933","9783642314940"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-31494-0_32","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]}}}