{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,2]],"date-time":"2025-04-02T19:10:23Z","timestamp":1743621023582,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642314933"},{"type":"electronic","value":"9783642314940"}],"license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-31494-0_37","type":"book-chapter","created":{"date-parts":[[2012,6,27]],"date-time":"2012-06-27T13:28:40Z","timestamp":1340803720000},"page":"327-336","source":"Crossref","is-referenced-by-count":4,"title":["A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts"],"prefix":"10.1007","author":[{"given":"Bapi","family":"Kar","sequence":"first","affiliation":[]},{"given":"Susmita","family":"Sur-Kolay","sequence":"additional","affiliation":[]},{"given":"Sridhar H.","family":"Rangarajan","sequence":"additional","affiliation":[]},{"given":"Chittaranjan R.","family":"Mandal","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"37_CR1","unstructured":"Cormen, T., et al.: Introduction to Algorithms, 3rd edn. MIT Press (2009)"},{"issue":"2","key":"37_CR2","doi-asserted-by":"publisher","first-page":"231","DOI":"10.1145\/544536.544537","volume":"7","author":"P. Dasgupta","year":"2002","unstructured":"Dasgupta, P., et al.: Monotone Bipartitioning Problem in a Planar Point Set with Applications to VLSI. ACM Transactions on Design Automation of Electronic Systems\u00a07(2), 231\u2013248 (2002)","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"37_CR3","doi-asserted-by":"crossref","unstructured":"Guruswamy, M., Wong, D.: Channel Routing Order for Building-Block Layout with Rectilinear Modules. In: Proc. of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 184\u2013187 (1988)","DOI":"10.1109\/ICCAD.1988.122490"},{"issue":"5","key":"37_CR4","doi-asserted-by":"publisher","first-page":"1019","DOI":"10.1142\/S0218126604001854","volume":"13","author":"S. Majumdar","year":"2004","unstructured":"Majumdar, S., et al.: On Finding a Staircase Channel with Minimum Crossing Nets in a VLSI Floorplan. Journal of Circuits, Systems and Computers\u00a013(5), 1019\u20131038 (2004)","journal-title":"Journal of Circuits, Systems and Computers"},{"issue":"1","key":"37_CR5","doi-asserted-by":"crossref","first-page":"7","DOI":"10.1145\/1188275.1188282","volume":"12","author":"S. Majumdar","year":"2007","unstructured":"Majumdar, S., et al.: Hierarchical Partitioning of VLSI Floorplans by Staircases. ACM Transactions on Design Automation of Electronic Systems\u00a012(1), Article 7 (2007)","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"37_CR6","unstructured":"Parquet FloorPlanner, Rev-4.5, University of Michigan (2006), http:\/\/vlsicad.eecs.umich.edu\/BK\/parquet"},{"key":"37_CR7","doi-asserted-by":"crossref","unstructured":"Sherwani, N.: Algorithms for VLSI Physical Design Automation. Kluwer Academic Publishers (1993)","DOI":"10.1007\/978-1-4757-2219-2"},{"key":"37_CR8","doi-asserted-by":"crossref","unstructured":"Sur-Kolay, S., Bhattacharya, B.: The cycle structure of channel graphs in non-sliceable floorplans and a unified algorithm for feasible routing order. In: Proc. of IEEE International Conference on Computer Design (ICCD), pp. 524\u2013529 (1991)","DOI":"10.1109\/ICCD.1991.139964"},{"issue":"12","key":"37_CR9","doi-asserted-by":"publisher","first-page":"1533","DOI":"10.1109\/43.552086","volume":"15","author":"H. Yang","year":"1996","unstructured":"Yang, H., Wong, F.: Efficient network flow based min-cut balanced partitioning. IEEE Transactions on Computer Aided Design and Integrated Circuits and Systems\u00a015(12), 1533\u20131540 (1996)","journal-title":"IEEE Transactions on Computer Aided Design and Integrated Circuits and Systems"}],"container-title":["Lecture Notes in Computer Science","Progress in VLSI Design and Test"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-31494-0_37","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,2]],"date-time":"2025-04-02T18:45:01Z","timestamp":1743619501000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-31494-0_37"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642314933","9783642314940"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-31494-0_37","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]}}}