{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,2]],"date-time":"2025-04-02T19:10:21Z","timestamp":1743621021695,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":4,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642314933"},{"type":"electronic","value":"9783642314940"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-31494-0_46","type":"book-chapter","created":{"date-parts":[[2012,6,27]],"date-time":"2012-06-27T13:28:40Z","timestamp":1340803720000},"page":"367-369","source":"Crossref","is-referenced-by-count":0,"title":["Design of Combinational and Sequential Circuits Using Novel Feedthrough Logic"],"prefix":"10.1007","author":[{"given":"Sauvagya Ranjan","family":"Sahoo","sequence":"first","affiliation":[]},{"given":"Kamala Kanta","family":"Mahapatra","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"46_CR1","doi-asserted-by":"crossref","unstructured":"Vangal, S., Hoskote, Y., Somasekhar, D., Erraguntla, V., Howard, J., Ruhl, G., Veeramachaneni, V., Finan, D., Mathew, S., Borkar, N.: A 5-GHz floating point multiply-accumulator in 90-nm dual VT CMOS. In: Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, pp. 334\u2013335 (2003)","DOI":"10.1109\/ISSCC.2003.1234322"},{"key":"46_CR2","doi-asserted-by":"crossref","unstructured":"Mathew, S., Anders, M., Bloechel, B., Nguyen, T., Krishnamurthy, R., Borkar, S.: A 4 GHz 300 mW64b integer execution ALU with dual supply voltages in 90nm CMOS. In: IEEE Int. Solid State Cir. Conf., pp. 162\u2013163 (2004)","DOI":"10.1109\/JSSC.2004.838019"},{"key":"46_CR3","volume-title":"Digital Integrated Circuits: A Design perspective","author":"J.M. Rabaey","year":"2002","unstructured":"Rabaey, J.M., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits: A Design perspective, 2nd edn. Prentice-Hall, Upper saddle River (2002)","edition":"2"},{"issue":"6","key":"46_CR4","doi-asserted-by":"publisher","first-page":"489","DOI":"10.1109\/TCSII.2007.891759","volume":"54","author":"V. Navarro-Botello","year":"2007","unstructured":"Navarro-Botello, V., Montiel-Nelson, J.A., Nooshabadi, S.: Analysis of high performance fast feed through logic families in CMOS. IEEE Trans. Cir. & Syst. II\u00a054(6), 489\u2013493 (2007)","journal-title":"IEEE Trans. Cir. & Syst. II"}],"container-title":["Lecture Notes in Computer Science","Progress in VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-31494-0_46.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,2]],"date-time":"2025-04-02T18:45:08Z","timestamp":1743619508000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-31494-0_46"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642314933","9783642314940"],"references-count":4,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-31494-0_46","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]}}}