{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,2]],"date-time":"2025-04-02T19:10:16Z","timestamp":1743621016502,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":22,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642314933"},{"type":"electronic","value":"9783642314940"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-31494-0_54","type":"book-chapter","created":{"date-parts":[[2012,6,27]],"date-time":"2012-06-27T13:28:40Z","timestamp":1340803720000},"page":"393-405","source":"Crossref","is-referenced-by-count":2,"title":["Power Problems in VLSI Circuit Testing"],"prefix":"10.1007","author":[{"given":"Farhana","family":"Rashid","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vishwani D.","family":"Agrawal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"54_CR1","unstructured":"Agrawal, P., Agrawal, V.D.: On Improving the Efficiency of Monte Carlo Test Generation. In: Digest of 5th International Fault Tolerant Computing Symp., Paris, France, pp. 205\u2013209 (June 1975)"},{"key":"54_CR2","doi-asserted-by":"publisher","first-page":"691","DOI":"10.1109\/T-C.1975.224289","volume":"C-24","author":"P. Agrawal","year":"1975","unstructured":"Agrawal, P., Agrawal, V.D.: Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Networks. IEEE Trans. Computers\u00a0C-24, 691\u2013695 (1975)","journal-title":"IEEE Trans. Computers"},{"key":"54_CR3","doi-asserted-by":"publisher","first-page":"664","DOI":"10.1109\/TC.1976.1674670","volume":"C-25","author":"P. Agrawal","year":"1976","unstructured":"Agrawal, P., Agrawal, V.D.: On Monte Carlo Testing of Logic Tree Networks. IEEE Trans. Computers\u00a0C-25, 664\u2013667 (1976)","journal-title":"IEEE Trans. Computers"},{"key":"54_CR4","unstructured":"Bushnell, M.L., Agrawal, V.D.: Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Springer (2000)"},{"issue":"3","key":"54_CR5","doi-asserted-by":"publisher","first-page":"265","DOI":"10.1147\/rd.273.0265","volume":"27","author":"E.B. Eichelberger","year":"1983","unstructured":"Eichelberger, E.B., Lindbloom, E.: Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test. IBM Jour. Research and Development\u00a027(3), 265\u2013272 (1983)","journal-title":"IBM Jour. Research and Development"},{"key":"54_CR6","doi-asserted-by":"crossref","unstructured":"Girard, P.: Low Power Testing of VLSI Circuits: Problems and Solutions. In: Proc. First IEEE Symp. Quality Electronic Design (ISQED), pp. 173\u2013179 (March 2000)","DOI":"10.1109\/ISQED.2000.838871"},{"issue":"3","key":"54_CR7","doi-asserted-by":"publisher","first-page":"80","DOI":"10.1109\/MDT.2002.1003802","volume":"19","author":"P. Girard","year":"2002","unstructured":"Girard, P.: Survey of Low-Power Testing of VLSI Circuits. IEEE Design & Test of Computers\u00a019(3), 80\u201390 (2002)","journal-title":"IEEE Design & Test of Computers"},{"key":"54_CR8","doi-asserted-by":"crossref","unstructured":"Hartmann, J., Kemnitz, G.: How to Do Weighted Random Testing for BIST. In: Proc. IEEE\/ACM International Conf. Computer-Aided Design, pp. 568\u2013571 (November 1993)","DOI":"10.1109\/ICCAD.1993.580116"},{"key":"54_CR9","doi-asserted-by":"crossref","unstructured":"Hsu, F., Butler, K., Patel, J.H.: A Case Study on the Implementation of Illinois Scan Architecture. In: Proc. International Test Conf., pp. 538\u2013547 (2001)","DOI":"10.1109\/TEST.2001.966672"},{"issue":"8","key":"54_CR10","doi-asserted-by":"publisher","first-page":"904","DOI":"10.1109\/12.536233","volume":"45","author":"A. Majumder","year":"1996","unstructured":"Majumder, A.: On Evaluating and Optimizing Weights for Weighted Random Pattern Testing. IEEE Trans. Computers\u00a045(8), 904\u2013916 (1996)","journal-title":"IEEE Trans. Computers"},{"key":"54_CR11","doi-asserted-by":"crossref","first-page":"310","DOI":"10.1109\/43.205010","volume":"12","author":"F. Najm","year":"1993","unstructured":"Najm, F.: Transition Density: A New Measure of Activity in Digital Circuits. IEEE Trans. CAD\u00a012, 310\u2013323 (1993)","journal-title":"IEEE Trans. CAD"},{"key":"54_CR12","doi-asserted-by":"crossref","unstructured":"Rajski, J., Tyszer, J., Mrugalski, G., Nadeau-Dostie, B.: Test Generator with Preselected Toggling for Low Power Built-In Self-Test. In: Proc. 30th IEEE VLSI Test Symp., pp. 1\u20136 (April 2012)","DOI":"10.1109\/VTS.2012.6231071"},{"key":"54_CR13","unstructured":"Rashid, F.: Controlled Transition Density Based Power Constrained Scan-BIST with Reduced Test Time. Master\u2019s thesis, Auburn University, Alabama, USA (May 2012); A talk based on this thesis was presented in a student forum at the 21st IEEE North Atlantic Test Workshop, May 10 (2012)"},{"key":"54_CR14","unstructured":"Shanmugasundaram, P.: Test Time Optimization in Scan Circuits. Master\u2019s thesis, Auburn University, Alabama, USA"},{"key":"54_CR15","doi-asserted-by":"crossref","unstructured":"Shanmugasundaram, P., Agrawal, V.D.: Dynamic Scan Clock Control for Test Time Reduction Maintaining Peak Power Limit. In: Proc. 29th IEEE VLSI Test Symp., pp. 248\u2013253 (May 2011)","DOI":"10.1109\/VTS.2011.5783729"},{"key":"54_CR16","doi-asserted-by":"crossref","unstructured":"Shanmugasundaram, P., Agrawal, V.D.: Dynamic Scan Clock Control in BIST Circuits. In: Proc. Joint IEEE Int. Conf. on Industrial Electronics and 43rd Southeastern Symp. on System Theory, pp. 237\u2013242 (March 2011)","DOI":"10.1109\/SSST.2011.5753813"},{"key":"54_CR17","doi-asserted-by":"crossref","unstructured":"Shanmugasundaram, P., Agrawal, V.D.: Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock. In: Proc. 25th International Conf. VLSI Design, pp. 448\u2013453 (January 2012)","DOI":"10.1109\/VLSID.2012.112"},{"key":"54_CR18","unstructured":"Stroud, C.E.: AUSIM - Auburn University SIMulator, http:\/\/www.eng.auburn.edu\/users\/strouce\/ausim.html (accessed on March 6, 2012)"},{"key":"54_CR19","unstructured":"Stroud, C.E.: A Designer\u2019s Guide to Built-In Self-Test. Springer (2002)"},{"key":"54_CR20","doi-asserted-by":"crossref","unstructured":"Tehranipoor, M., Nourani, M., Ahmed, N.: Low Transition LFSR for BIST-Based Application. In: Proc. 14th IEEE Asian Test Symposium, pp. 138\u2013143 (December 2005)","DOI":"10.1109\/ATS.2005.77"},{"key":"54_CR21","unstructured":"Udavanshi, S.: Design of Low Power and High Fault Coverage Test Pattern Generator for BIST. Master\u2019s thesis, Thaper University, Patiala, India (July 2011)"},{"key":"54_CR22","unstructured":"Wang, S.: Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST. In: Proc. International Test Conf., pp. 834\u2013843 (2002)"}],"container-title":["Lecture Notes in Computer Science","Progress in VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-31494-0_54.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,2]],"date-time":"2025-04-02T18:45:41Z","timestamp":1743619541000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-31494-0_54"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642314933","9783642314940"],"references-count":22,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-31494-0_54","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2012]]}}}