{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:42:08Z","timestamp":1750243328083,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":59,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642327698"},{"type":"electronic","value":"9783642327704"}],"license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-32770-4_2","type":"book-chapter","created":{"date-parts":[[2012,9,26]],"date-time":"2012-09-26T00:28:20Z","timestamp":1348619300000},"page":"10-33","source":"Crossref","is-referenced-by-count":14,"title":["High Performance SoC Design Using Magnetic Logic and Memory"],"prefix":"10.1007","author":[{"given":"Weisheng","family":"Zhao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lionel","family":"Torres","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lu\u00eds Vit\u00f3rio","family":"Cargnini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Raphael Martins","family":"Brum","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yue","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yoann","family":"Guillemenet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gilles","family":"Sassatelli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yahya","family":"Lakys","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jacques-Olivier","family":"Klein","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Etiemble","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dafin\u00e9","family":"Ravelosona","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Claude","family":"Chappert","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"2_CR1","volume-title":"CMOS VLSI Design: A Circuits and Systems Perspective","author":"N. Weste","year":"2010","unstructured":"Weste, N., Harris, D.: CMOS VLSI Design: A Circuits and Systems Perspective, 4th edn. Addison-Wesley Publishing Company, USA (2010)","edition":"4"},{"key":"2_CR2","unstructured":"Kang, S., Leblebici, Y.: CMOS digital integrated circuits: analysis and design. McGraw-Hill series in electrical engineering. McGraw-Hill (1999)"},{"issue":"12","key":"2_CR3","doi-asserted-by":"publisher","first-page":"68","DOI":"10.1109\/MC.2003.1250885","volume":"36","author":"N. Kim","year":"2003","unstructured":"Kim, N., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J., Irwin, M., Kandemir, M., Narayanan, V.: Leakage current: Moore\u2019s law meets static power. Computer\u00a036(12), 68\u201375 (2003)","journal-title":"Computer"},{"key":"2_CR4","doi-asserted-by":"crossref","unstructured":"Slaughter, J., Dave, R., Durlam, M., Kerszykowski, G., Smith, K., Nagel, K., Feil, B., Calder, J., DeHerrera, M., Garni, B., Tehrani, S.: High speed toggle mram with mgo-based tunnel junctions. In: IEEE International Electron Devices Meeting, IEDM Technical Digest, pp. 873\u2013876 (December 2005)","DOI":"10.1109\/IEDM.2005.1609496"},{"key":"2_CR5","doi-asserted-by":"crossref","unstructured":"Hoya, K., Takashima, D., Shiratake, S., Ogiwara, R., Miyakawa, T., Shiga, H., Doumae, S., Ohtsuki, S., Kumura, Y., Shuto, S., Ozaki, T., Yamakawa, K., Kunishima, I., Nitayama, A., Fujii, S.: A 64mb chain feram with quad-bl architecture and 200mb\/s burst mode. In: IEEE International on Solid-State Circuits Conference, ISSCC 2006, Digest of Technical Papers, pp. 459\u2013466 (February 2006)","DOI":"10.1109\/ISSCC.2006.1696078"},{"issue":"12","key":"2_CR6","doi-asserted-by":"publisher","first-page":"2201","DOI":"10.1109\/JPROC.2010.2070050","volume":"98","author":"H. Wong","year":"2010","unstructured":"Wong, H., Raoux, S., Kim, S., Liang, J., Reifenberg, J., Rajendran, B., Asheghi, M., Goodson, K.: Phase change memory. Proceedings of the IEEE\u00a098(12), 2201\u20132227 (2010)","journal-title":"Proceedings of the IEEE"},{"key":"2_CR7","doi-asserted-by":"crossref","unstructured":"Kund, M., Beitel, G., Pinnow, C.U., Rohr, T., Schumann, J., Symanczyk, R., Ufert, K.D., Muller, G.: Conductive bridging ram (cbram): an emerging non-volatile memory technology scalable to sub 20nm. In: IEEE International Electron Devices Meeting, IEDM Technical Digest, pp. 754\u2013757 (December 2005)","DOI":"10.1109\/IEDM.2005.1609463"},{"issue":"11","key":"2_CR8","doi-asserted-by":"publisher","first-page":"813","DOI":"10.1038\/nmat2024","volume":"6","author":"C. Chappert","year":"2007","unstructured":"Chappert, C., Fert, A., Van Dau, F.N.: The emergence of spin eletronics in data storage. Nature Materials\u00a06(11), 813\u2013823 (2007)","journal-title":"Nature Materials"},{"issue":"5546","key":"2_CR9","doi-asserted-by":"publisher","first-page":"1488","DOI":"10.1126\/science.1065389","volume":"294","author":"S.A. Wolf","year":"2001","unstructured":"Wolf, S.A., Awschalom, D.D., Buhrman, R.A., Daughton, J.M., Von Moln\u00e1r, S., Roukes, M.L., Chtchelkanova, A.Y., Treger, D.M.: Spintronics: a spin-based electronics vision for the future. Science\u00a0294(5546), 1488\u20131495 (2001)","journal-title":"Science"},{"key":"2_CR10","unstructured":"Freescale: Freescale leads industry in commercializing mram technology; 4 mbit mram memory product now in volume production (July 2006), http:\/\/investors.freescale.com\/phoenix.zhtml?c=175261&p=irol-newsArticle&ID=880031"},{"issue":"16","key":"2_CR11","first-page":"165218","volume":"19","author":"I.L. Prejbeanu","year":"2007","unstructured":"Prejbeanu, I.L., Kerekes, M., Sousa, R.C., Sibuet, H., Redon, O., Dieny, B., Nozi\u00e8res, J.P.: Thermally assisted mram. Journal of Physics: Condensed Matter\u00a019(16), 165218 (2007)","journal-title":"Journal of Physics: Condensed Matter"},{"issue":"1","key":"2_CR12","doi-asserted-by":"publisher","first-page":"81","DOI":"10.1147\/rd.501.0081","volume":"50","author":"J.Z. Sun","year":"2006","unstructured":"Sun, J.Z.: Spin angular momentum transfer in current-perpendicular nanomagnetic junctions. IBM Journal of Research and Development\u00a050(1), 81\u2013100 (2006)","journal-title":"IBM Journal of Research and Development"},{"key":"2_CR13","doi-asserted-by":"crossref","unstructured":"Kawahara, T., Takemura, R., Miura, K., Hayakawa, J., Ikeda, S., Lee, Y., Sasaki, R., Goto, Y., Ito, K., Meguro, I., Matsukura, F., Takahashi, H., Matsuoka, H., Ohno, H.: 2mb spin-transfer torque ram (spram) with bit-by-bit bidirectional current write and parallelizing-direction current read. In: IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, pp. 480\u2013617 (February 2007)","DOI":"10.1109\/ISSCC.2007.373503"},{"issue":"5873","key":"2_CR14","doi-asserted-by":"publisher","first-page":"190","DOI":"10.1126\/science.1145799","volume":"320","author":"S.S.P. Parkin","year":"2008","unstructured":"Parkin, S.S.P., Hayashi, M., Thomas, L.: Magnetic domain-wall racetrack memory. Science\u00a0320(5873), 190\u2013194 (2008)","journal-title":"Science"},{"key":"2_CR15","doi-asserted-by":"crossref","unstructured":"Lin, C., Kang, S., Wang, Y., Lee, K., Zhu, X., Chen, W., Li, X., Hsu, W., Kao, Y., Liu, M., Lin, Y., Nowak, M., Yu, N., Tran, L.: 45nm low power cmos logic compatible embedded stt mram utilizing a reverse-connection 1t\/1mtj cell. In: 2009 IEEE International Electron Devices Meeting (IEDM), pp. 258\u2013259 (December 2009)","DOI":"10.1109\/IEDM.2009.5424368"},{"key":"2_CR16","doi-asserted-by":"crossref","unstructured":"Tsuchida, K., Inaba, T., Fujita, K., Ueda, Y., Shimizu, T., Asao, Y., Kajiyama, T., Iwayama, M., Sugiura, K., Ikegawa, S., Kishi, T., Kai, T., Amano, M., Shimomura, N., Yoda, H., Watanabe, Y.: A 64mb mram with clamped-reference and adequate-reference schemes. In: 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 258\u2013259 (February 2010)","DOI":"10.1109\/ISSCC.2010.5433948"},{"key":"2_CR17","unstructured":"ITRS: International roadmap for semiconductors 2007 and 2008 update (2007), http:\/\/www.itrs.net\/Links\/2007ITRS\/Home2007.html"},{"issue":"9","key":"2_CR18","doi-asserted-by":"publisher","first-page":"6674","DOI":"10.1063\/1.372806","volume":"87","author":"W.C. Black","year":"2000","unstructured":"Black, W.C., Das, B.: Programmable logic using giant-magnetoresistance and spin-dependent tunneling devices (invited). Journal of Applied Physics\u00a087(9), 6674\u20136679 (2000)","journal-title":"Journal of Applied Physics"},{"key":"2_CR19","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1596543.1596548","volume":"9","author":"W. Zhao","year":"2009","unstructured":"Zhao, W., Belhaire, E., Chappert, C., Mazoyer, P.: Spin transfer torque (stt)-mram\u2013based runtime reconfiguration fpga circuit. ACM Trans. Embed. Comput. Syst.\u00a09, 14:1\u201314:16 (2009)","journal-title":"ACM Trans. Embed. Comput. Syst."},{"key":"2_CR20","doi-asserted-by":"crossref","unstructured":"Guillemenet, Y., Torres, L., Sassatelli, G., Bruchon, N., Hassoune, I.: A non-volatile run-time fpga using thermally assisted switching mrams. In: International Conference on Field Programmable Logic and Applications, FPL 2008, pp. 421\u2013426 (September 2008)","DOI":"10.1109\/FPL.2008.4629974"},{"key":"2_CR21","unstructured":"Suzuki, D., Natsui, M., Ikeda, S., Hasegawa, H., Miura, K., Hayakawa, J., Endoh, T., Ohno, H., Hanyu, T.: Fabrication of a nonvolatile lookup-table circuit chip using magneto\/semiconductor-hybrid structure for an immediate-power-up field programmable gate array. In: 2009 Symposium on VLSI Circuits, pp. 80\u201381 (June 2009)"},{"issue":"9","key":"2_CR22","doi-asserted-by":"crossref","first-page":"090204","DOI":"10.1143\/JJAP.49.090204","volume":"49","author":"S. Yamamoto","year":"2010","unstructured":"Yamamoto, S., Sugahara, S.: Nonvolatile delay flip-flop based on spin-transistor architecture and its power-gating applications. Japanese Journal of Applied Physics\u00a049(9), 090204 (2010)","journal-title":"Japanese Journal of Applied Physics"},{"key":"2_CR23","doi-asserted-by":"crossref","unstructured":"Sakimura, N., Sugibayashi, T., Nebashi, R., Kasai, N.: Nonvolatile magnetic flip-flop for standby-power-free socs. In: Custom Integrated Circuits Conference, CICC 2008, pp. 355\u2013358. IEEE (September 2008)","DOI":"10.1109\/CICC.2008.4672095"},{"key":"2_CR24","doi-asserted-by":"publisher","first-page":"155","DOI":"10.1145\/1785481.1785519","volume-title":"Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI, GLSVLSI 2010","author":"S. Chaudhuri","year":"2010","unstructured":"Chaudhuri, S., Zhao, W., Klein, J.O., Chappert, C., Mazoyer, P.: Design of embedded mram macros for memory-in-logic applications. In: Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI, GLSVLSI 2010, pp. 155\u2013158. ACM, New York (2010)"},{"key":"2_CR25","doi-asserted-by":"crossref","unstructured":"Zhao, W., Belhaire, E., Dieny, B., Prenat, G., Chappert, C.: Tas-mram based non-volatile fpga logic circuit. In: International Conference on Field-Programmable Technology, ICFPT 2007, pp. 153\u2013160 (December 2007)","DOI":"10.1109\/FPT.2007.4439244"},{"key":"2_CR26","doi-asserted-by":"publisher","first-page":"211","DOI":"10.1049\/iet-cdt.2009.0019","volume":"4","author":"Y. Guillemenet","year":"2010","unstructured":"Guillemenet, Y., Torres, L., Sassatelli, G.: Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories. Computers Digital Techniques, IET\u00a04, 211\u2013226 (2010)","journal-title":"Computers Digital Techniques, IET"},{"key":"2_CR27","doi-asserted-by":"crossref","first-page":"057206","DOI":"10.1103\/PhysRevLett.100.057206","volume":"100","author":"T. Devolder","year":"2008","unstructured":"Devolder, T., Hayakawa, J., Ito, K., Takahashi, H., Ikeda, S., Crozat, P., Zerounian, N., Kim, J.V., Chappert, C., Ohno, H.: Single-shot time-resolved measurements of nanosecond-scale spin-transfer induced switching: Stochastic versus deterministic aspects. Phys. Rev. Lett.\u00a0100, 057206 (2008)","journal-title":"Phys. Rev. Lett."},{"issue":"9","key":"2_CR28","doi-asserted-by":"publisher","first-page":"721","DOI":"10.1038\/nmat2804","volume":"9","author":"S. Ikeda","year":"2010","unstructured":"Ikeda, S., Miura, K., Yamamoto, H., Mizunuma, K., Gan, H.D., Endo, M., Kanai, S., Hayakawa, J., Matsukura, F., Ohno, H.: A perpendicular-anisotropy cofeb\u2013mgo magnetic tunnel junction. Nature Materials\u00a09(9), 721\u2013724 (2010)","journal-title":"Nature Materials"},{"issue":"10","key":"2_CR29","doi-asserted-by":"publisher","first-page":"3784","DOI":"10.1109\/TMAG.2009.2024325","volume":"45","author":"W. Zhao","year":"2009","unstructured":"Zhao, W., Chappert, C., Javerliac, V., Noziere, J.P.: High speed, high stability and low power sensing amplifier for mtj\/cmos hybrid logic circuits. IEEE Transactions on Magnetics\u00a045(10), 3784\u20133787 (2009)","journal-title":"IEEE Transactions on Magnetics"},{"key":"2_CR30","doi-asserted-by":"crossref","unstructured":"Faber, L.B., Zhao, W., Klein, J.O., Devolder, T., Chappert, C.: Dynamic compact model of spin-transfer torque based magnetic tunnel junction (mtj). In: 4th International Conference on Design Technology of Integrated Systems in Nanoscal Era, DTIS 2009, pp. 130\u2013135 (April 2009)","DOI":"10.1109\/DTIS.2009.4938040"},{"key":"2_CR31","doi-asserted-by":"crossref","unstructured":"Nepal, K., Bahar, R., Mundy, J., Patterson, W., Zaslavsky, A.: Designing mrf based error correcting circuits for memory elements. In: Proceedings of Design, Automation and Test in Europe, DATE 2006, vol.\u00a01, pp. 1\u20132 (March 2006)","DOI":"10.1109\/DATE.2006.244144"},{"issue":"4\/5\/6\/7\/8","key":"2_CR32","doi-asserted-by":"publisher","first-page":"591","DOI":"10.1504\/IJNT.2010.031735","volume":"7","author":"B. Dieny","year":"2010","unstructured":"Dieny, B., Sousa, R.C., Herault, J., Papusoi, C., Prenat, G., Ebels, U., Houssameddine, D., Rodmacq, B., Auffret, S., Prejbeanu, L.D.B., et al.: Spin-transfer effect and its use in spintronic components. International Journal of Nanotechnology\u00a07(4\/5\/6\/7\/8), 591 (2010)","journal-title":"International Journal of Nanotechnology"},{"issue":"1","key":"2_CR33","doi-asserted-by":"publisher","first-page":"368","DOI":"10.1186\/1556-276X-6-368","volume":"6","author":"W. Zhao","year":"2011","unstructured":"Zhao, W., Duval, J., Klein, J., Chappert, C.: A compact model for magnetic tunnel junction (mtj) switched by thermally assisted spin transfer torque (tas + stt). Nanoscale Research Letters\u00a06(1), 368 (2011)","journal-title":"Nanoscale Research Letters"},{"issue":"2","key":"2_CR34","doi-asserted-by":"publisher","first-page":"22501","DOI":"10.1063\/1.3536482","volume":"98","author":"D.C. Worledge","year":"2011","unstructured":"Worledge, D.C., Hu, G., Abraham, D.W., Sun, J.Z., Trouilloud, P.L., Nowak, J., Brown, S., Gaidis, M.C., O\u2019Sullivan, E.J., Robertazzi, R.P.: Spin torque switching of perpendicular ta|cofeb|mgo-based magnetic tunnel junctions. Applied Physics Letters\u00a098(2), 22501 (2011)","journal-title":"Applied Physics Letters"},{"key":"2_CR35","doi-asserted-by":"crossref","unstructured":"Sun, Z., Bi, X., Li, H., Wong, W., Ong, Z., Zhu, X., Wu, W.: Multi-retention level stt-ram cache designs with a dynamic refresh scheme. In: Proceedings of the 44th Annual ACM\/IEEE International Symposium on Microarchitecture, MICRO 44, Porto Alegre, Brazil, pp. 329\u2013338. IEEE Computer Society (December 2011)","DOI":"10.1145\/2155620.2155659"},{"key":"2_CR36","unstructured":"Xilinx, I.: Spartan-3 fpga family data sheet (December 2009), http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds099.pdf"},{"key":"2_CR37","unstructured":"Torres, L., Guillemenet, Y., Ahmed, S.Z.: A dynamic reconfigurable mram based fpga. In: ERSA 2010 Keynote Paper, p. 10 (2010)"},{"key":"2_CR38","doi-asserted-by":"crossref","unstructured":"Zhao, W., Belhaire, E., Javerliac, V., Chappert, C., Dieny, B.: A non-volatile flip-flop in magnetic fpga chip. In: International Conference on Design and Test of Integrated Systems in Nanoscale Technology, DTIS 2006, pp. 323\u2013326 (September 2006)","DOI":"10.1109\/DTIS.2006.1708702"},{"key":"2_CR39","unstructured":"Kang, S.H.: Embedded stt-mram for mobile applications: Enabling advanced chip architectures. In: Non-Volatile Memories Workshop, San Diego, CA, USA (April 2010)"},{"issue":"2","key":"2_CR40","doi-asserted-by":"publisher","first-page":"161","DOI":"10.1109\/TC.2007.21","volume":"56","author":"L. Kothari","year":"2007","unstructured":"Kothari, L., Carter, N.P.: Architecture of a self-checkpointing microprocessor that incorporates nanomagnetic devices. IEEE Transactions on Computers\u00a056(2), 161\u2013173 (2007)","journal-title":"IEEE Transactions on Computers"},{"issue":"4","key":"2_CR41","doi-asserted-by":"publisher","first-page":"266","DOI":"10.1038\/nnano.2010.31","volume":"5","author":"B. Behin-Aein","year":"2010","unstructured":"Behin-Aein, B., Deepanjan Datta, S.S., Datt, S.: Proposal for an all-spin logic device with built-in memory. Nature Nanotechnology\u00a05(4), 266\u2013270 (2010)","journal-title":"Nature Nanotechnology"},{"issue":"5741","key":"2_CR42","doi-asserted-by":"publisher","first-page":"1688","DOI":"10.1126\/science.1108813","volume":"309","author":"D.A. Allwood","year":"2005","unstructured":"Allwood, D.A., Xiong, G., Faulkner, C.C., Atkinson, D., Petit, D., Cowburn, R.P.: Magnetic domain-wall logic. Science\u00a0309(5741), 1688\u20131692 (2005)","journal-title":"Science"},{"issue":"9","key":"2_CR43","doi-asserted-by":"publisher","first-page":"91301","DOI":"10.1143\/APEX.1.091301","volume":"1","author":"S. Matsunaga","year":"2008","unstructured":"Matsunaga, S., Hayakawa, J., Ikeda, S., Miura, K., Hasegawa, H., Endoh, T., Ohno, H., Hanyu, T.: Fabrication of a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions. Applied Physics Express\u00a01(9), 091301 (2008)","journal-title":"Applied Physics Express"},{"key":"2_CR44","doi-asserted-by":"crossref","unstructured":"Sun, G., Dong, X., Xie, Y., Li, J., Chen, Y.: A novel architecture of the 3d stacked mram l2 cache for cmps. In: IEEE 15th International Symposium on High Performance Computer Architecture, HPCA 2009, pp. 239\u2013249 (February 2009)","DOI":"10.1109\/HPCA.2009.4798259"},{"issue":"22","key":"2_CR45","doi-asserted-by":"publisher","first-page":"1493","DOI":"10.1049\/el.2010.2039","volume":"46","author":"Y. Lakys","year":"2010","unstructured":"Lakys, Y., Zhao, W., Klein, J.O., Chappert, C.: Low power, high reliability magnetic flip-flop. Electronics Letters\u00a046(22), 1493\u20131494 (2010)","journal-title":"Electronics Letters"},{"key":"2_CR46","doi-asserted-by":"publisher","first-page":"13","DOI":"10.1145\/268806.268810","volume":"25","author":"D. Burger","year":"1997","unstructured":"Burger, D., Austin, T.M.: The simplescalar tool set, version 2.0. SIGARCH Comput. Archit. News\u00a025, 13\u201325 (1997)","journal-title":"SIGARCH Comput. Archit. News"},{"key":"2_CR47","first-page":"330","volume-title":"Proceedings of the 30th Annual ACM\/IEEE International Symposium on Microarchitecture, MICRO 30","author":"C. Lee","year":"1997","unstructured":"Lee, C., Potkonjak, M., Mangione-Smith, W.H.: Mediabench: a tool for evaluating and synthesizing multimedia and communicatons systems. In: Proceedings of the 30th Annual ACM\/IEEE International Symposium on Microarchitecture, MICRO 30, pp. 330\u2013335. IEEE Computer Society, Washington, DC (1997)"},{"key":"2_CR48","unstructured":"Gaisler, A.: Leon3 multiprocessing cpu core (February 2010), http:\/\/www.gaisler.com\/doc\/leon3_product_sheet.pdf"},{"key":"2_CR49","series-title":"IFIP AICT","first-page":"10","volume-title":"VLSI-SoC 2011","author":"W. Zhao","year":"2012","unstructured":"Zhao, W., Torres, L., Cargnini, L.V., Brum, R.M., Zhang, Y., Guillemenet, Y., Sassatelli, G., Lakys, Y., Klein, J.-O., Etiemble, D., Ravelosona, D., Chappert, C.: High Performance SoC Design Using Magnetic Logic and Memory. In: Mir, S., et al. (eds.) VLSI-SoC 2011. IFIP AICT, vol.\u00a0379, pp. 10\u201333. Springer, Heidelberg (2012)"},{"key":"2_CR50","unstructured":"Mackay, K.: Tas, tas+stt-mram and magnetic logic unit, Property of Crocus Technology. Non authorized Publication (November 2011)"},{"key":"2_CR51","unstructured":"JC-42.3: Double data rate (ddr) sdram standard. Standard, JEDEC (2008), http:\/\/www.jedec.org\/standards-documents\/docs\/jesd-79f"},{"key":"2_CR52","doi-asserted-by":"crossref","unstructured":"Powell, M., Agarwal, A., Vijaykumar, T., Falsafi, B., Roy, K.: Reducing set-associative cache energy via way-prediction and selective direct-mapping. In: Proceedings of 34th ACM\/IEEE International Symposium on Microarchitecture, MICRO-34, pp. 54\u201365 (2001)","DOI":"10.1109\/MICRO.2001.991105"},{"key":"2_CR53","unstructured":"Hennessy, J.L., Patterson, D.A.: Computer architecture: a quantitative approach, 4th edn., vol.\u00a01. Elsevier - Morgan Kaufmann - Denise E. M. Penrose (2007)"},{"key":"2_CR54","unstructured":"Patterson, D.A., Hennessy, J.L.: Computer organization and design: the hardware\/software interface (2005)"},{"key":"2_CR55","doi-asserted-by":"crossref","unstructured":"Boschma, B., Burns, D., Chin, R., Fiduccia, N., Hu, C., Reed, M., Rueth, T., Schumacher, F., Shen, V.: A 30 mips vlsi cpu. In: 36th IEEE International Solid-State Circuits Conference, ISSCC 1989, Digest of Technical Papers, pp. 82\u201383 (1989)","DOI":"10.1109\/ISSCC.1989.48191"},{"issue":"11","key":"2_CR56","doi-asserted-by":"publisher","first-page":"1650","DOI":"10.1109\/4.726553","volume":"33","author":"H. Nambu","year":"1998","unstructured":"Nambu, H., Kanetani, K., Yamasaki, K., Higeta, K., Usami, M., Fujimura, Y., Ando, K., Kusunoki, T., Yamaguchi, K., Homma, N.: A 1.8-ns access, 550-mhz, 4.5-mb cmos sram. IEEE Journal of Solid-State Circuits\u00a033(11), 1650\u20131658 (1998)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"2_CR57","doi-asserted-by":"crossref","unstructured":"Alvarez, J., Barkin, E., Chao, C.C., Johnson, B., D\u2019Addeo, M., Lassandro, F., Nicoletta, G., Patel, P., Reed, P., Reid, D., Sanchez, H., Siegel, J., Snyder, M., Sullivan, S., Taylor, S., Vo, M.: 450 mhz powerpctm microprocessor with enhanced instruction set and copper interconnect. In: 1999 IEEE International Solid-State Circuits Conference, ISSCC 1999, Digest of Technical Papers, pp. 96\u201397 (1999)","DOI":"10.1109\/ISSCC.1999.759141"},{"key":"2_CR58","doi-asserted-by":"crossref","unstructured":"Gharachorloo, K., Gupta, A., Hennessy, J.: Performance evaluation of memory consistency models for shared-memory multiprocessors. In: Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, United States. ASPLOS-IV, pp. 245\u2013257. ACM, New York (1991), http:\/\/doi.acm.org\/10.1145\/106972.106997 , doi:10.1145\/106972.106997, ISBN: 0-89791-380-9","DOI":"10.1145\/106972.106997"},{"key":"2_CR59","doi-asserted-by":"crossref","unstructured":"Gutierrez, A., Dreslinski, R., Wenisch, T., Mudge, T., Saidi, A., Emmons, C., Paver, N.: Full-system analysis and characterization of interactive smartphone applications. In: 2011 IEEE International Symposium on Workload Characterization (IISWC), pp. 81\u201390 (2011)","DOI":"10.1109\/IISWC.2011.6114205"}],"container-title":["IFIP Advances in Information and Communication Technology","VLSI-SoC: Advanced Research for Systems on Chip"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-32770-4_2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T13:14:10Z","timestamp":1744204450000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-32770-4_2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642327698","9783642327704"],"references-count":59,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-32770-4_2","relation":{},"ISSN":["1868-4238","1861-2288"],"issn-type":[{"type":"print","value":"1868-4238"},{"type":"electronic","value":"1861-2288"}],"subject":[],"published":{"date-parts":[[2012]]}}}